Greek64
5d9acb6f41
QSYS does not allow to change the VHDL version of processed files. All respective files have to have a comment directive forcing the VHDL version.
56 lines
1.3 KiB
VHDL
56 lines
1.3 KiB
VHDL
-- altera vhdl_input_version vhdl_2008
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-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.math_pkg.all;
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use work.rtps_package.all;
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-- Test synthesis of 3-way min comparison
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entity test2 is
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port (
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clk : in std_logic;
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reset : in std_logic;
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t1 : in TIME_TYPE;
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t2 : in TIME_TYPE;
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t3 : in TIME_TYPE;
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t : in TIME_TYPE;
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t_out : out TIME_TYPE
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);
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end entity;
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architecture arch of test2 is
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function min_time(t1, t2, t3, t : TIME_TYPE) return TIME_TYPE is
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variable ret : TIME_TYPE;
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begin
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if (not (t1 <= t)) then
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ret := t1;
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end if;
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if (not (t2 <= t) and t2 < ret) then
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ret := t2;
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end if;
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if (not (t3 <= t) and t3 < ret) then
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ret := t3;
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end if;
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return ret;
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end function;
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begin
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process (all)
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begin
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if rising_edge(clk) then
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if (reset = '1') then
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t_out <= TIME_INVALID;
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else
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t_out <= min_time(t1,t2,t3,t);
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end if;
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end if;
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end process;
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end architecture;
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