385 lines
18 KiB
VHDL
385 lines
18 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library Testbench_Lib2;
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use Testbench_Lib2.rtps_package.all;
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use Testbench_Lib2.user_config.all;
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use Testbench_Lib2.rtps_config_package.all;
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use Testbench_Lib2.rtps_test_package.all;
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use Testbench_Lib2.Type1_package.all;
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entity L2_Testbench_Lib2 is
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port (
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-- SYSTEM
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clk : in std_logic;
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reset : in std_logic;
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time : in TIME_TYPE;
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-- INPUT
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empty : in std_logic;
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rd : out std_logic;
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data_in : in std_logic_vector(WORD_WIDTH-1 downto 0);
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-- OUTPUT
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data_out : out std_logic_vector(WORD_WIDTH-1 downto 0);
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wr : out std_logic;
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full : in std_logic;
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-- TO USER ENTITY
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start_user : in std_logic;
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ack_user : out std_logic;
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opcode_user : in DDS_WRITER_OPCODE_TYPE;
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instance_handle_user : in INSTANCE_HANDLE_TYPE;
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source_ts_user : in TIME_TYPE;
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max_wait_user : in DURATION_TYPE;
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done_user : out std_logic;
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return_code_user : out std_logic_vector(RETURN_CODE_WIDTH-1 downto 0);
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ready_out_user : in std_logic;
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valid_out_user : out std_logic;
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data_out_user : out std_logic_vector(WORD_WIDTH-1 downto 0);
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last_word_out_user : out std_logic;
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-- Communication Status
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status_user : out std_logic_vector(STATUS_KIND_WIDTH-1 downto 0);
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-- ###GENERATED START###
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id : in std_logic_vector(CDR_LONG_WIDTH-1 downto 0);
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a : in std_logic_vector(CDR_LONG_WIDTH-1 downto 0);
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-- ###GENERATED END###
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encode_done : out std_logic
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);
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end entity;
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architecture arch of L2_Testbench_Lib2 is
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type ENDPOINT_DATA_TYPE is array (0 to NUM_ENDPOINTS) of std_logic_vector(WORD_WIDTH downto 0);
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-- INTERCONNECT
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signal start_wr_dds, ack_wr_dds, done_wr_dds, ready_out_wr_dds, valid_out_wr_dds, last_word_out_wr_dds, ready_in_wr_dds, valid_in_wr_dds, last_word_in_wr_dds : std_logic;
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signal opcode_wr_dds : DDS_WRITER_OPCODE_TYPE;
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signal instance_handle_wr_dds : INSTANCE_HANDLE_TYPE;
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signal source_ts_wr_dds : TIME_TYPE;
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signal max_wait_wr_dds : DURATION_TYPE;
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signal return_code_wr_dds : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0);
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signal data_in_wr_dds, data_out_wr_dds : std_logic_vector(WORD_WIDTH-1 downto 0);
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signal status_wr_dds : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0);
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signal start_dds_rtps, ack_dds_rtps, done_dds_rtps, get_data_dds_rtps, valid_out_dds_rtps, ready_out_dds_rtps, last_word_out_dds_rtps, liveliness_assertion_dds_rtps, data_available_dds_rtps : std_logic;
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signal data_out_dds_rtps : std_logic_vector(WORD_WIDTH-1 downto 0);
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signal opcode_dds_rtps : HISTORY_CACHE_OPCODE_TYPE;
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signal ret_dds_rtps : HISTORY_CACHE_RESPONSE_TYPE;
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signal seq_nr_dds_rtps : SEQUENCENUMBER_TYPE;
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signal cc_instance_handle_dds_rtps : INSTANCE_HANDLE_TYPE;
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signal cc_kind_dds_rtps : CACHE_CHANGE_KIND_TYPE;
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signal cc_source_timestamp_dds_rtps : TIME_TYPE;
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signal cc_seq_nr_dds_rtps : SEQUENCENUMBER_TYPE;
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signal empty_rh, full_rh, rd_rh, wr_rh : std_logic_vector(0 to NUM_ENDPOINTS);
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signal data_in_rh, data_out_rh : ENDPOINT_DATA_TYPE;
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signal empty_rtps, full_rtps, rd_rtps, wr_rtps, alive_sig_rtps : std_logic_vector(0 to NUM_ENDPOINTS);
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signal data_in_rtps, data_out_rtps : ENDPOINT_DATA_TYPE;
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signal wr_rtps_out, rd_rtps_out, full_rtps_out, empty_rtps_out : std_logic_vector(0 to NUM_ENDPOINTS);
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signal data_out_rtps_out, data_in_rtps_out : ENDPOINT_DATA_TYPE;
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signal last_word_out_rbe : std_logic;
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signal data_out_rbe : std_logic_vector(WORD_WIDTH-1 downto 0);
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signal last_word_out_rh_be_s, last_word_out_rh_ue_s : std_logic;
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signal data_out_rh_be_s, data_out_rh_ue_s : std_logic_vector(WORD_WIDTH-1 downto 0);
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signal data_rtps_out_s : RTPS_OUT_DATA_TYPE;
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signal last_word_rtps_out_s : std_logic_vector(0 to NUM_ENDPOINTS);
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begin
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Type1_writer_wrapper_w_inst : entity Testbench_Lib2.Type1_writer_wrapper(arch)
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port map (
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-- SYSTEM
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clk => clk,
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reset => reset,
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-- FROM DDS WRITER
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start_dds => start_wr_dds,
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ack_dds => ack_wr_dds,
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opcode_dds => opcode_wr_dds,
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instance_handle_dds => instance_handle_wr_dds,
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source_ts_dds => source_ts_wr_dds,
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max_wait_dds => max_wait_wr_dds,
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done_dds => done_wr_dds,
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return_code_dds => return_code_wr_dds,
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ready_out_dds => ready_out_wr_dds,
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valid_out_dds => valid_out_wr_dds,
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data_out_dds => data_out_wr_dds,
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last_word_out_dds => last_word_out_wr_dds,
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ready_in_dds => ready_in_wr_dds,
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valid_in_dds => valid_in_wr_dds,
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data_in_dds => data_in_wr_dds,
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last_word_in_dds => last_word_in_wr_dds,
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-- Communication Status
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status_dds => status_wr_dds,
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-- TO USER ENTITY
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start_user => start_user,
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ack_user => ack_user,
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opcode_user => opcode_user,
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instance_handle_user => instance_handle_user,
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source_ts_user => source_ts_user,
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max_wait_user => max_wait_user,
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done_user => done_user,
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return_code_user => return_code_user,
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ready_out_user => ready_out_user,
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valid_out_user => valid_out_user,
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data_out_user => data_out_user,
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last_word_out_user => last_word_out_user,
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-- Communication Status
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status_user => status_user,
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-- ###GENERATED START###
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id => id,
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a => a,
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-- ###GENERATED END###
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encode_done => encode_done
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);
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dds_writer_w_inst : entity Testbench_Lib2.dds_writer(arch)
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generic map (
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HISTORY_QOS => ENDPOINT_HISTORY_QOS(0),
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DEADLINE_QOS => ENDPOINT_DEADLINE_QOS(0),
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LIFESPAN_QOS => ENDPOINT_LIFESPAN_QOS(0),
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LEASE_DURATION => ENDPOINT_LEASE_DURATION(0),
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WITH_KEY => ENDPOINT_WITH_KEY(0),
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MAX_SAMPLES => ENDPOINT_MAX_SAMPLES(0),
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MAX_INSTANCES => ENDPOINT_MAX_INSTANCES(0),
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MAX_SAMPLES_PER_INSTANCE => ENDPOINT_MAX_SAMPLES_PER_INSTANCE(0),
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PAYLOAD_FRAME_SIZE => MAX_TYPE1_SIZE
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)
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port map (
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-- SYSTEM
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clk => clk,
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reset => reset,
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time => time,
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-- TO/FROM RTPS ENDPOINT
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start_rtps => start_dds_rtps,
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opcode_rtps => opcode_dds_rtps,
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ack_rtps => ack_dds_rtps,
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done_rtps => done_dds_rtps,
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ret_rtps => ret_dds_rtps,
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seq_nr_rtps => seq_nr_dds_rtps,
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get_data_rtps => get_data_dds_rtps,
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data_out_rtps => data_out_dds_rtps,
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valid_out_rtps => valid_out_dds_rtps,
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ready_out_rtps => ready_out_dds_rtps,
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last_word_out_rtps => last_word_out_dds_rtps,
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liveliness_assertion => liveliness_assertion_dds_rtps,
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data_available => data_available_dds_rtps,
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-- Cache Change
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cc_instance_handle => cc_instance_handle_dds_rtps,
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cc_kind => cc_kind_dds_rtps,
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cc_source_timestamp => cc_source_timestamp_dds_rtps,
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cc_seq_nr => cc_seq_nr_dds_rtps,
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-- TO/FROM USER ENTITY
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start_dds => start_wr_dds,
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ack_dds => ack_wr_dds,
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opcode_dds => opcode_wr_dds,
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instance_handle_dds => instance_handle_wr_dds,
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source_ts_dds => source_ts_wr_dds,
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max_wait_dds => max_wait_wr_dds,
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done_dds => done_wr_dds,
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return_code_dds => return_code_wr_dds,
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ready_in_dds => ready_out_wr_dds,
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valid_in_dds => valid_out_wr_dds,
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data_in_dds => data_out_wr_dds,
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last_word_in_dds => last_word_out_wr_dds,
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ready_out_dds => ready_in_wr_dds,
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valid_out_dds => valid_in_wr_dds,
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data_out_dds => data_in_wr_dds,
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last_word_out_dds => last_word_in_wr_dds,
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-- Communication Status
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status => status_wr_dds
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);
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rtps_writer_w_inst : entity Testbench_Lib2.rtps_writer(arch)
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generic map (
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RELIABILITY_QOS => ENDPOINT_RELIABILITY_QOS(0),
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LIVELINESS_QOS => ENDPOINT_LIVELINESS_QOS(0),
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DURABILITY_QOS => ENDPOINT_DURABILITY_QOS(0),
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DESTINATION_ORDER_QOS => ENDPOINT_DESTINATION_ORDER_QOS(0),
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ACKNACK_RESPONSE_DELAY => ENDPOINT_ACKNACK_RESPONSE_DELAY(0),
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ACKNACK_SUPPRESSION_DELAY => ENDPOINT_ACKNACK_SUPPRESSION_DELAY(0),
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LEASE_DURATION => ENDPOINT_LEASE_DURATION(0),
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HEARTBEAT_PERIOD => ENDPOINT_HEARTBEAT_PERIOD(0),
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ENTITYID => ENTITYID(0),
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WITH_KEY => ENDPOINT_WITH_KEY(0),
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PUSH_MODE => ENDPOINT_PUSH_MODE(0),
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INLINE_QOS => gen_inline_qos(0),
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MAX_REMOTE_ENDPOINTS => 5
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)
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port map (
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-- SYSTEM
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clk => clk,
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reset => reset,
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time => time,
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-- FROM RTPS_HANDLER (USER TRAFFIC)
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empty_user => empty_rh(0),
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rd_user => rd_rh(0),
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data_in_user => data_out_rh(0)(WORD_WIDTH-1 downto 0),
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last_word_in_user => data_out_rh(0)(WORD_WIDTH),
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-- FROM RTPS_BUILTIN_ENDPOINT (META TRAFFIC)
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empty_meta => empty_rtps(0),
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rd_meta => rd_rtps(0),
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data_in_meta => data_out_rtps(0)(WORD_WIDTH-1 downto 0),
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last_word_in_meta => data_out_rtps(0)(WORD_WIDTH),
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-- TO RTPS_BUILTIN_ENDPOINT (META TRAFFIC)
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alive_sig => alive_sig_rtps(0),
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-- RTPS OUTPUT
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wr_ro => wr_rtps_out(0),
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full_ro => full_rtps_out(0),
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data_out_ro => data_in_rtps_out(0)(WORD_WIDTH-1 downto 0),
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last_word_out_ro => data_in_rtps_out(0)(WORD_WIDTH),
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-- FROM HC
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liveliness_assertion => liveliness_assertion_dds_rtps,
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data_available => data_available_dds_rtps,
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start_hc => start_dds_rtps,
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opcode_hc => opcode_dds_rtps,
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ack_hc => ack_dds_rtps,
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seq_nr_hc => seq_nr_dds_rtps,
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done_hc => done_dds_rtps,
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ret_hc => ret_dds_rtps,
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get_data_hc => get_data_dds_rtps,
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data_in_hc => data_out_dds_rtps,
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valid_in_hc => valid_out_dds_rtps,
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ready_in_hc => ready_out_dds_rtps,
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last_word_in_hc => last_word_out_dds_rtps,
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cc_instance_handle => cc_instance_handle_dds_rtps,
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cc_kind => cc_kind_dds_rtps,
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cc_source_timestamp => cc_source_timestamp_dds_rtps,
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cc_seq_nr => cc_seq_nr_dds_rtps
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);
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rtps_builtin_endpoint_w_inst : entity Testbench_Lib2.rtps_builtin_endpoint(arch)
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generic map (
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MAX_REMOTE_PARTICIPANTS => 5
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)
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port map (
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clk => clk,
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reset => reset,
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time => time,
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-- FROM RTPS HANDLER
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empty => empty_rh(NUM_ENDPOINTS),
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rd => rd_rh(NUM_ENDPOINTS),
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data_in => data_out_rh(NUM_ENDPOINTS)(WORD_WIDTH-1 downto 0),
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last_word_in => data_out_rh(NUM_ENDPOINTS)(WORD_WIDTH),
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-- FROM USER ENDPOINTS
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alive => alive_sig_rtps(0 to NUM_ENDPOINTS-1),
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-- TO USER ENDPOINTS
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full_ue => full_rtps(0 to NUM_ENDPOINTS-1),
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wr_ue => wr_rtps(0 to NUM_ENDPOINTS-1),
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data_out_ue => data_out_rbe,
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last_word_out_ue => last_word_out_rbe,
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-- TO RTPS OUT
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full_ro => full_rtps_out(NUM_ENDPOINTS),
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wr_ro => wr_rtps_out(NUM_ENDPOINTS),
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data_out_ro => data_in_rtps_out(NUM_ENDPOINTS)(WORD_WIDTH-1 downto 0),
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last_word_out_ro => data_in_rtps_out(NUM_ENDPOINTS)(WORD_WIDTH)
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);
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data_in_rtps(0 to NUM_ENDPOINTS-1) <= (others => (last_word_out_rbe & data_out_rbe));
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rtps_handler_w_inst : entity Testbench_Lib2.rtps_handler(arch)
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port map (
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-- SYSTEM
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clk => clk,
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reset => reset,
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-- INPUT
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empty => empty,
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rd => rd,
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data_in => data_in,
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-- TO RTPS BUILTIN ENDPOINT
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full_be => full_rh(NUM_ENDPOINTS),
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wr_be => wr_rh(NUM_ENDPOINTS),
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data_out_be => data_out_rh_be_s,
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last_word_out_be => last_word_out_rh_be_s,
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-- TO RTPS ENDPOINT
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full_ue => full_rh(0 to NUM_ENDPOINTS-1),
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wr_ue => wr_rh(0 to NUM_ENDPOINTS-1),
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data_out_ue => data_out_rh_ue_s,
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last_word_out_ue => last_word_out_rh_ue_s
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);
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data_in_rh <= (NUM_ENDPOINTS => (last_word_out_rh_be_s & data_out_rh_be_s), others => (last_word_out_rh_ue_s & data_out_rh_ue_s));
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rtps_out_w_inst : entity Testbench_Lib2.rtps_out(arch)
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port map (
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clk => clk,
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reset => reset,
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-- INPUT
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data_in => data_rtps_out_s,
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last_word_in => last_word_rtps_out_s,
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rd => rd_rtps_out,
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empty => empty_rtps_out,
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-- OUTPUT
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data_out => data_out,
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wr => wr,
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full => full
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);
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rh_fifo_gen : for i in 0 to NUM_ENDPOINTS generate
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begin
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fifo_inst : configuration Testbench_Lib2.FWFT_FIFO_cfg
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generic map (
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FIFO_DEPTH => 2,
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DATA_WIDTH => WORD_WIDTH+1
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)
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port map
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(
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reset => reset,
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clk => clk,
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data_in => data_in_rh(i),
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write => wr_rh(i),
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read => rd_rh(i),
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data_out => data_out_rh(i),
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empty => empty_rh(i),
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full => full_rh(i),
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free => open
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);
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end generate;
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rtps_out_fifo_gen : for i in 0 to NUM_ENDPOINTS generate
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begin
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fifo_inst : configuration Testbench_Lib2.FWFT_FIFO_cfg
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generic map (
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FIFO_DEPTH => 2,
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DATA_WIDTH => WORD_WIDTH+1
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)
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port map
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(
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reset => reset,
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clk => clk,
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data_in => data_in_rtps_out(i),
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write => wr_rtps_out(i),
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read => rd_rtps_out(i),
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data_out => data_out_rtps_out(i),
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empty => empty_rtps_out(i),
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full => full_rtps_out(i),
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free => open
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);
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data_rtps_out_s(i) <= data_out_rtps_out(i)(WORD_WIDTH-1 downto 0);
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last_word_rtps_out_s(i) <= data_out_rtps_out(i)(WORD_WIDTH);
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end generate;
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rtps_fifo_gen : for i in 0 to NUM_ENDPOINTS-1 generate
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begin
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fifo_inst : configuration Testbench_Lib2.FWFT_FIFO_cfg
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generic map (
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FIFO_DEPTH => 2,
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DATA_WIDTH => WORD_WIDTH+1
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)
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port map
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(
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reset => reset,
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clk => clk,
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data_in => data_in_rtps(i),
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write => wr_rtps(i),
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read => rd_rtps(i),
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data_out => data_out_rtps(i),
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empty => empty_rtps(i),
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full => full_rtps(i),
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free => open
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);
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end generate;
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end architecture; |