Greek
6e20b8958d
Add VHDL configuration for single_port_ram and FWFT_FIFO
...
Allow single_port_ram and FWFT_FIFO to have Altera specific
architectures.
2021-12-09 19:43:56 +01:00
Greek
b47d409f13
Make codebase Quartus synthesizable
...
Remove non-Quartus-supported VHDL 2008 features.
Remove inferred Latches.
Add test Entities to see resulting hw synthesis of various code
segments.
2021-12-07 13:05:24 +01:00
Greek
63465e8e30
Remove default signal initialization from entire codebase
2021-11-19 18:50:18 +01:00
Greek
4830645a5a
Move key_holder inside the DDS Entities
2021-11-19 12:00:07 +01:00
Greek
e87d84ba24
Modify ports of rtps_builtin_endpoint according to port naming convention
...
The ports to rtps_out from the rtps_reader and rtps_writer entities were
also modified to apply a uniform naming.
2021-11-18 16:44:42 +01:00
Greek
399bd2bbda
Modify ports of rtps_handler according to port naming convention
2021-11-18 12:20:20 +01:00
Greek
9cc4907a2f
Add complete Level2 System Test
...
Using seperately compiled Libraries we interconnect two systems, and
test their communication and interaction.
A bug in rtps_builtin_endpoint was fixed (were if only the SUB data was
to be sent, it was never actually sent).
2021-11-17 14:23:53 +01:00
