Greek64
5d9acb6f41
QSYS does not allow to change the VHDL version of processed files. All respective files have to have a comment directive forcing the VHDL version.
47 lines
1.2 KiB
VHDL
47 lines
1.2 KiB
VHDL
-- altera vhdl_input_version vhdl_2008
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-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library altera_mf;
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use altera_mf.altera_mf_components.all;
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use work.math_pkg.all;
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architecture altera of FWFT_FIFO is
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signal used_sig : std_logic_vector(log2c(FIFO_DEPTH)-1 downto 0);
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begin
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-- XXX: Possible Worst Case Path
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free <= FIFO_DEPTH - to_integer(unsigned(used_sig));
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scfifo_component : scfifo
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generic map (
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add_ram_output_register => "OFF",
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intended_device_family => "Cyclone V",
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lpm_numwords => FIFO_DEPTH,
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lpm_showahead => "ON",
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lpm_type => "scfifo",
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lpm_width => DATA_WIDTH,
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lpm_widthu => log2c(FIFO_DEPTH),
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overflow_checking => "ON",
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underflow_checking => "ON",
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use_eab => "ON"
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)
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port map (
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clock => clk,
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sclr => reset,
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data => data_in,
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rdreq => read,
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wrreq => write,
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empty => empty,
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full => full,
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q => data_out,
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usedw => used_sig
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);
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end architecture;
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