981ca09149
The instantiation of the KEY related entities is moved outside the DDS Endpoints (Currently only changed in DDS Writer). Define new KEY_HOLDER entity that is responsible for all Key related type-specific code. Fix syntax of DDS Writer, and misc code refactoring.
475 lines
18 KiB
VHDL
475 lines
18 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library osvvm; -- Utility Library
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context osvvm.OsvvmContext;
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use work.rtps_package.all;
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use work.user_config.all;
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use work.rtps_config_package.all;
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use work.rtps_test_package.all;
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-- This testbench tests the metatraffic operation behaviour of the RTPS Writer. (Remote Endpoint matching and Memory behaviour)
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-- This testbench is using external names to access the memory of the rtps_reader directly and check the contents at the supposed locations.
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-- This testbench covers following:
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-- * Mathing Endpoint
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-- * Memory Full Behaviour
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-- * Unmatching Endpoint
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-- * Unmatching Participant
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-- * Updating previously matched Endpoint
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-- * Unknown Metatraffic Operation
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entity L0_rtps_writer_test1_vrkdp is
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end entity;
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architecture testbench of L0_rtps_writer_test1_vrkdp is
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-- *CONSTANT DECLARATION*
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constant MAX_REMOTE_ENDPOINTS : natural := 3;
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-- *TYPE DECLARATION*
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type TEST_STAGE_TYPE is (IDLE, BUSY);
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type TEST_RAM_TYPE is array (0 to (MAX_REMOTE_ENDPOINTS*READER_ENDPOINT_FRAME_SIZE_A)-1) of std_logic_vector(WORD_WIDTH-1 downto 0);
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-- *SIGNAL DECLARATION*
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signal clk, empty_user, empty_meta, rd_meta, last_word_in_meta : std_logic := '0';
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signal reset : std_logic := '1';
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signal data_in_meta : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
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signal start_hc : std_logic := '0';
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signal stim_stage : TEST_STAGE_TYPE := IDLE;
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shared variable stimulus : TEST_PACKET_TYPE := EMPTY_TEST_PACKET;
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signal packet_sent : std_logic := '0';
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signal cnt_stim : natural := 0;
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signal start : std_logic := '0';
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shared variable SB_mem : work.ScoreBoardPkg_MemoryTest.ScoreBoardPType;
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signal stim_done, mem_check_done, test_done : std_logic := '0';
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-- *FUNCTION DECLARATION*
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procedure wait_on_sent is
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begin
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wait until rising_edge(packet_sent);
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end procedure;
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procedure wait_on_mem_check is
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begin
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if (mem_check_done /= '1') then
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wait until mem_check_done = '1';
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end if;
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end procedure;
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procedure wait_on_completion is
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begin
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if (test_done /= '1') then
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wait until test_done = '1';
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end if;
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end procedure;
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begin
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-- Unit Under Test
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uut : entity work.rtps_writer(arch)
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generic map (
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RELIABILTY_QOS => RELIABLE_RELIABILITY_QOS,
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LIVELINESS_QOS => AUTOMATIC_LIVELINESS_QOS,
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DURABILITY_QOS => VOLATILE_DURABILITY_QOS,
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DESTINATION_ORDER_QOS => BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS,
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ACKNACK_RESPONSE_DELAY => DURATION_ZERO,
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ACKNACK_SUPPRESSION_DELAY => DURATION_ZERO,
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LEASE_DURATION => DURATION_INFINITE,
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HEARTBEAT_PERIOD => DURATION_INFINITE,
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ENTITYID => DEFAULT_WRITER_ENTITYID,
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WITH_KEY => TRUE,
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PUSH_MODE => TRUE,
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INLINE_QOS => gen_inline_qos(NUM_READERS+7),
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MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS
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)
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port map (
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clk => clk,
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reset => reset,
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time => TIME_ZERO,
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empty_user => '1',
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rd_user => open,
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data_in_user => (others => '0'),
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last_word_in_user => '0',
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empty_meta => empty_meta or packet_sent,
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rd_meta => rd_meta,
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data_in_meta => data_in_meta,
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last_word_in_meta => last_word_in_meta,
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alive_sig => open,
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wr_rtps => open,
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full_rtps => '0',
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last_word_out_rtps => open,
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data_out_rtps => open,
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liveliness_assertion => '0',
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data_available => '0',
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start_hc => start_hc,
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opcode_hc => open,
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ack_hc => '0',
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seq_nr_hc => open,
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done_hc => '0',
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ret_hc => ERROR,
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get_data_hc => open,
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data_in_hc => (others => '0'),
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valid_in_hc => '0',
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ready_in_hc => open,
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last_word_in_hc => '0',
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cc_instance_handle => HANDLE_NIL,
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cc_kind => ALIVE,
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cc_source_timestamp => TIME_INVALID,
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cc_seq_nr => SEQUENCENUMBER_UNKNOWN
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);
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stimulus_prc : process
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variable RV : RandomPType;
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variable p0, p1, participant : PARTICIPANT_DATA_TYPE := DEFAULT_PARTICIPANT_DATA;
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variable e0, e1, e2, e3, endpoint : ENDPOINT_DATA_TYPE := DEFAULT_ENDPOINT_DATA;
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-- Wrapper to use procedure as function
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impure function gen_rand_loc_2 return LOCATOR_TYPE is
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variable ret : LOCATOR_TYPE := EMPTY_LOCATOR;
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begin
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gen_rand_loc(RV, ret);
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return ret;
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end function;
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impure function gen_rand_guid_prefix return GUIDPREFIX_TYPE is
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variable ret : GUIDPREFIX_TYPE;
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begin
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ret := (0 => RV.RandSlv(WORD_WIDTH), 1 => RV.RandSlv(WORD_WIDTH), 2 => RV.RandSlv(WORD_WIDTH));
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return ret;
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end function;
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procedure start_test is
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begin
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start <= '1';
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wait until rising_edge(clk);
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start <= '0';
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wait until rising_edge(clk);
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end procedure;
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begin
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SetAlertLogName("rtps_writer - (Volatile, Reliable, Keyed, By Reception Timestamp, Push Mode) - Level 0 - Metatraffic Handling");
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SetAlertEnable(FAILURE, TRUE);
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SetAlertEnable(ERROR, TRUE);
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SetAlertEnable(WARNING, TRUE);
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SetLogEnable(DEBUG, FALSE);
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SetLogEnable(PASSED, FALSE);
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SetLogEnable(INFO, TRUE);
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RV.InitSeed(RV'instance_name);
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p0.guidPrefix := gen_rand_guid_prefix;
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p1.guidPrefix := gen_rand_guid_prefix;
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-- Endpoint 1
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e0 := DEFAULT_ENDPOINT_DATA;
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e0.participant := p0;
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e0.entityid := RV.RandSlv(ENTITYID_WIDTH);
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e0.unicastLocatorList := (numLocators => int(1,CDR_LONG_WIDTH), locator => (0 => gen_rand_loc_2, others => EMPTY_LOCATOR));
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-- Endpoint 2
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e1 := DEFAULT_ENDPOINT_DATA;
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e1.participant := p0;
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e1.entityid := RV.RandSlv(ENTITYID_WIDTH);
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e1.unicastLocatorList := (numLocators => int(1,CDR_LONG_WIDTH), locator => (0 => gen_rand_loc_2, others => EMPTY_LOCATOR));
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e1.reliability := BEST_EFFORT_RELIABILITY_QOS;
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-- Endpoint 3
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e2 := DEFAULT_ENDPOINT_DATA;
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e2.participant := p1;
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e2.entityid := RV.RandSlv(ENTITYID_WIDTH);
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e2.unicastLocatorList := (numLocators => int(1,CDR_LONG_WIDTH), locator => (0 => gen_rand_loc_2, others => EMPTY_LOCATOR));
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e2.expectsInlineQoS(0) := '1';
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e2.durability := TRANSIENT_LOCAL_DURABILITY_QOS;
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e2.reliability := BEST_EFFORT_RELIABILITY_QOS;
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-- Endpoint 4
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e3 := DEFAULT_ENDPOINT_DATA;
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e3.participant := p1;
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e3.entityid := RV.RandSlv(ENTITYID_WIDTH);
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e3.unicastLocatorList := (numLocators => int(1,CDR_LONG_WIDTH), locator => (0 => gen_rand_loc_2, others => EMPTY_LOCATOR));
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e3.expectsInlineQoS(0) := '1';
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Log("Initiating Test", INFO);
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stim_done <= '0';
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start <= '0';
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reset <= '1';
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wait until rising_edge(clk);
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wait until rising_edge(clk);
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reset <= '0';
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Log("Insert Endpoint 0 Participant 0", INFO);
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endpoint := e0;
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endpoint.nr := 0;
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endpoint.match := MATCH;
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gen_endpoint_match_frame(endpoint, stimulus);
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SB_mem.Push(gen_reader_endpoint_mem_frame_a(endpoint));
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start_test;
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wait_on_sent;
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stimulus := EMPTY_TEST_PACKET;
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wait_on_mem_check;
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-- MEMORY STATE [p0e0,0,0]
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Log("Insert Endpoint 1 Participant 0", INFO);
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endpoint := e1;
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endpoint.nr := 1;
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endpoint.match := MATCH;
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gen_endpoint_match_frame(endpoint, stimulus);
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SB_mem.Push(gen_reader_endpoint_mem_frame_a(endpoint));
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start_test;
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wait_on_sent;
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stimulus := EMPTY_TEST_PACKET;
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wait_on_mem_check;
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-- MEMORY STATE [p0e0,p0e1,0]
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Log("Insert Endpoint 2 Participant 1", INFO);
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endpoint := e2;
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endpoint.nr := 2;
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endpoint.match := MATCH;
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gen_endpoint_match_frame(endpoint, stimulus);
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SB_mem.Push(gen_reader_endpoint_mem_frame_a(endpoint));
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start_test;
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wait_on_sent;
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stimulus := EMPTY_TEST_PACKET;
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wait_on_mem_check;
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-- MEMORY STATE [p0e0,p0e1,p1e2]
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Log("Ignore Endpoint 3 Participant 1 [Memory Full]", INFO);
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endpoint := e3;
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endpoint.match := MATCH;
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gen_endpoint_match_frame(endpoint, stimulus);
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-- Re-check Mem-State
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endpoint := e0;
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endpoint.nr := 0;
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endpoint.match := MATCH;
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SB_mem.Push(gen_reader_endpoint_mem_frame_a(endpoint));
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endpoint := e1;
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endpoint.nr := 1;
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endpoint.match := MATCH;
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SB_mem.Push(gen_reader_endpoint_mem_frame_a(endpoint));
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endpoint := e2;
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endpoint.nr := 2;
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endpoint.match := MATCH;
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SB_mem.Push(gen_reader_endpoint_mem_frame_a(endpoint));
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start_test;
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wait_on_sent;
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stimulus := EMPTY_TEST_PACKET;
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wait_on_mem_check;
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-- MEMORY STATE [p0e0,p0e1,p1e3]
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Log("Remove Endpoint 2 Participant 1", INFO);
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endpoint := e2;
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endpoint.nr := 2;
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endpoint.match := UNMATCH;
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gen_endpoint_match_frame(endpoint, stimulus);
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SB_mem.Push(gen_reader_endpoint_mem_frame_a(endpoint));
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start_test;
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wait_on_sent;
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stimulus := EMPTY_TEST_PACKET;
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wait_on_mem_check;
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-- MEMORY STATE [p0e0,p0e1,0]
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Log("Insert Endpoint 3 Participant 1", INFO);
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endpoint := e3;
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endpoint.nr := 2;
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endpoint.match := MATCH;
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gen_endpoint_match_frame(endpoint, stimulus);
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SB_mem.Push(gen_reader_endpoint_mem_frame_a(endpoint));
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start_test;
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wait_on_sent;
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stimulus := EMPTY_TEST_PACKET;
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wait_on_mem_check;
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-- MEMORY STATE [p0e0,p0e1,p1e3]
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Log("Remove Participant 0", INFO);
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participant := p0;
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participant.match := UNMATCH;
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gen_participant_match_frame(participant, stimulus);
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-- Remove Endpoint 0
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endpoint := e0;
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endpoint.nr := 0;
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endpoint.match := UNMATCH;
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SB_mem.Push(gen_reader_endpoint_mem_frame_a(endpoint));
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-- Remove Endpoint 1
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endpoint := e1;
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endpoint.nr := 1;
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endpoint.match := UNMATCH;
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SB_mem.Push(gen_reader_endpoint_mem_frame_a(endpoint));
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start_test;
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wait_on_sent;
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stimulus := EMPTY_TEST_PACKET;
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wait_on_mem_check;
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-- MEMORY STATE [0,0,p1e3]
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Log("Insert Endpoint 2 Participant 1", INFO);
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endpoint := e2;
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endpoint.nr := 0;
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endpoint.match := MATCH;
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gen_endpoint_match_frame(endpoint, stimulus);
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SB_mem.Push(gen_reader_endpoint_mem_frame_a(endpoint));
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start_test;
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wait_on_sent;
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stimulus := EMPTY_TEST_PACKET;
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wait_on_mem_check;
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-- MEMORY STATE [p1e2,0,p1e3]
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Log("Unknown Metatraffic Operation followed by insertion of Enpoint 0 Participant 0", INFO);
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for i in 0 to 9 loop
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stimulus.data(i) := RV.RandSlv(WORD_WIDTH);
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end loop;
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stimulus.last(9) := '1';
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stimulus.length := 10;
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endpoint := e0;
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endpoint.nr := 1;
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endpoint.match := MATCH;
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gen_endpoint_match_frame(endpoint, stimulus);
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-- Re-check Mem-State
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endpoint := e2;
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endpoint.nr := 0;
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endpoint.match := MATCH;
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SB_mem.Push(gen_reader_endpoint_mem_frame_a(endpoint));
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endpoint := e0;
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endpoint.nr := 1;
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endpoint.match := MATCH;
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SB_mem.Push(gen_reader_endpoint_mem_frame_a(endpoint));
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endpoint := e3;
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endpoint.nr := 2;
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endpoint.match := MATCH;
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SB_mem.Push(gen_reader_endpoint_mem_frame_a(endpoint));
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start_test;
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wait_on_sent;
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stimulus := EMPTY_TEST_PACKET;
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wait_on_mem_check;
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-- MEMORY STATE [p1e2,p0e0,p1e3]
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Log("Update Endpoint 2 Participant 1", INFO);
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endpoint := e2;
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endpoint.nr := 0;
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endpoint.match := MATCH;
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endpoint.unicastLocatorList := (numLocators => int(1,CDR_LONG_WIDTH), locator => (0 => gen_rand_loc_2, others => EMPTY_LOCATOR));
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gen_endpoint_match_frame(endpoint, stimulus);
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SB_mem.Push(gen_reader_endpoint_mem_frame_a(endpoint));
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start_test;
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wait_on_sent;
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stimulus := EMPTY_TEST_PACKET;
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wait_on_mem_check;
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-- MEMORY STATE [p1e2,p0e0,p1e3]
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stim_done <= '1';
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wait_on_completion;
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TranscriptOpen(RESULTS_FILE, APPEND_MODE);
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SetTranscriptMirror;
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ReportAlerts;
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TranscriptClose;
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std.env.stop;
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wait;
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end process;
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clock_prc : process
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begin
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clk <= '0';
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wait for 25 ns;
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clk <= '1';
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wait for 25 ns;
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end process;
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in_empty_prc : process
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begin
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empty_meta <= '0';
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wait until rd_meta = '1';
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wait until rising_edge(clk);
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empty_meta <= '1';
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wait until rising_edge(clk);
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end process;
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alert_prc : process(all)
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begin
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if rising_edge(clk) then
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alertif(empty_meta = '1' and rd_meta = '1', "Input FIFO read signal high while empty signal high", ERROR);
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alertif(start_hc = '1', "Unexpected History Cache Operation initiated", ERROR);
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end if;
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end process;
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input_prc : process(all)
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begin
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data_in_meta <= stimulus.data(cnt_stim);
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last_word_in_meta <= stimulus.last(cnt_stim);
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if rising_edge(clk) then
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if (reset = '1') then
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cnt_stim <= 0;
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stim_stage <= IDLE;
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packet_sent <= '1';
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else
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case (stim_stage) is
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when IDLE =>
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if (start = '1' and stimulus.length /= 0) then
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stim_stage <= BUSY;
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packet_sent <= '0';
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end if;
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when BUSY =>
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if (rd_meta = '1') then
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if (cnt_stim = stimulus.length-1) then
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stim_stage <= IDLE;
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packet_sent <= '1';
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cnt_stim <= 0;
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else
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cnt_stim <= cnt_stim + 1;
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end if;
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end if;
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end case;
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end if;
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end if;
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end process;
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done_proc : process(clk)
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begin
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if rising_edge(clk) then
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if (stim_done = '1' and SB_mem.empty) then
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test_done <= '1';
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else
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test_done <= '0';
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end if;
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end if;
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end process;
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mem_check_prc : process
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alias mem is <<signal uut.mem_ctrl_inst.ram_inst.mem : TEST_RAM_TYPE>>;
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alias mem_op_done is <<signal uut.mem_op_done : std_logic>>;
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alias idle_sig is <<signal uut.idle_sig : std_logic>>;
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variable reference : TEST_READER_ENDPOINT_MEMORY_FRAME_TYPE_A;
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begin
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mem_check_done <= '0';
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-- SAFEGUARD: (Prevent Fall-through Behavior)
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if (reset /= '0') then
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wait until reset = '0';
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end if;
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-- Wait for Packet to be sent
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wait until rising_edge(packet_sent);
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-- Wait for UUT IDLE state
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if (idle_sig /= '1') then
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wait until idle_sig = '1';
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end if;
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-- Wait for ongoing memory operation
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if (mem_op_done /= '1') then
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wait until mem_op_done = '1';
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end if;
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while (not SB_mem.empty) loop
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SB_mem.Pop(reference);
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for i in 0 to reference'length-1 loop
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AffirmIf(?? (mem(reference(i).addr) ?= reference(i).data), "Address: " & integer'image(reference(i).addr) & " Received: " & to_hstring(mem(reference(i).addr)) & " Expected: " & to_hstring(reference(i).data));
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end loop;
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end loop;
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-- Toggle High for one clock cycle
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mem_check_done <= '1';
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wait until rising_edge(clk);
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end process;
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watchdog : process
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begin
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wait for 1 ms;
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Alert("Test timeout", FAILURE);
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std.env.stop;
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end process;
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end architecture; |