46ca2228b6
Simple Dual Port (Read and Write Port), and True Dual Port RAM implementations, together with their respective Altera implementations were added. The 'arch' Architectures should have the same behaviour as the Altera Implementations (single_port_ram was modified to achieve that)
51 lines
1.5 KiB
VHDL
51 lines
1.5 KiB
VHDL
-- altera vhdl_input_version vhdl_2008
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-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity single_port_ram is
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generic (
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ADDR_WIDTH : natural := 8;
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DATA_WIDTH : natural := 12;
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MEMORY_DEPTH : natural := 256
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);
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port (
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clk : in std_logic;
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addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
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wen : in std_logic;
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ren : in std_logic;
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wr_data : in std_logic_vector(DATA_WIDTH-1 downto 0);
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rd_data : out std_logic_vector(DATA_WIDTH-1 downto 0)
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);
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end entity;
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architecture arch of single_port_ram is
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type RAM_TYPE is array (0 to MEMORY_DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
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signal mem : RAM_TYPE := (others => (others => '0'));
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begin
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ram_prc : process(all)
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begin
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if rising_edge(clk) then
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rd_data <= (others => '0');
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-- Read-During-Write not supported
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assert(wen = '1' nand ren = '1') severity FAILURE;
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if (wen = '1') then
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mem(to_integer(unsigned(addr))) <= wr_data;
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end if;
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if (ren = '1') then
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rd_data <= mem(to_integer(unsigned(addr)));
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end if;
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end if;
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end process;
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end architecture;
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