greek64/rtps-fpga
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a1e0297fcb
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John Daktylidis a1e0297fcb Add GHRD Quartus Project 
The Golden Hardware Reference Design (GHRD) is used to implement designs
with PS support.
The UDP/IP stack of the Linux running on the PS is used to move UDP packets
to/from the PL.
2023-07-23 14:12:50 +02:00
doc Documentation & Code Refactoring 2023-06-17 10:48:11 +02:00
sim Add moving_average VHDL Implementation 2023-06-24 00:02:02 +02:00
src Modified Type Size convention 2023-07-22 14:46:49 +02:00
syn Add GHRD Quartus Project 2023-07-23 14:12:50 +02:00
.gitattributes * Added DDS/RTPS Documentation 2020-05-10 19:31:49 +02:00
.gitignore Add GHRD Quartus Project 2023-07-23 14:12:50 +02:00
.gitmodules * Added OSVVM Library as Submodule 2020-11-15 20:34:39 +01:00
READ.txt Documentation & Code Refactoring 2023-06-17 10:48:11 +02:00
ros_action_Fibonacci_with_feedback2.rpt Convert rtps_writer to Vector Endpoint 2022-04-05 17:18:07 +02:00
ros_action_Fibonacci_with_feedback3.rpt Convert rtps_writer to Vector Endpoint 2022-04-05 17:18:07 +02:00
ros_action_Fibonacci_with_feedback4.rpt Convert rtps_reader to Vector Endpoint 2022-04-05 17:20:22 +02:00
ros_action_Fibonacci_with_feedback5.rpt Convert dds_writer to Vector Endpoint 2022-04-10 11:04:02 +02:00
ros_action_Fibonacci_with_feedback6.rpt TIMING CLOSURE: Split main FSM in dds_reader 2022-04-14 14:27:09 +02:00
ros_action_Fibonacci_with_feedback.rpt Add/Modify synthesis entities to synthesize Fibonacci_ros_action_server 2022-03-13 12:43:12 +01:00
ros_action_Fibonacci_with_feedback.txt TIMING CLOSURE: Split main FSM in dds_reader 2022-04-14 14:27:09 +02:00
ros_action_Fibonacci_without_feedback.rpt Add/Modify synthesis entities to synthesize Fibonacci_ros_action_server 2022-03-13 12:43:12 +01:00
VHDL-2008.txt Code Refactor 2021-05-15 20:39:56 +02:00