152 lines
4.9 KiB
VHDL
152 lines
4.9 KiB
VHDL
-- altera vhdl_input_version vhdl_2008
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-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.test_package.all;
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-- Test synthesis of array indexing
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entity test6 is
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port (
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clk : in std_logic;
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reset : in std_logic;
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input1 : in TEST_ENUM;
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input2 : in TEST_ENUM;
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input3 : in TEST_ENUM;
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input4 : in std_logic;
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input5 : in std_logic;
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output : out std_logic
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);
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end entity;
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architecture arch of test6 is
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type STAGE_TYPE is (IN1, IN2, IN3);
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signal stage : STAGE_TYPE;
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begin
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-- process (all)
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-- variable tmp_bool : boolean;
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-- begin
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-- if rising_edge(clk) then
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-- if (reset = '1') then
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-- output <= '0';
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-- else
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-- tmp_bool := TRUE;
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--
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-- case (input1) is
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-- when A =>
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-- if (input4 = '1') then
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-- tmp_bool := FALSE;
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-- end if;
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-- when B =>
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-- if (input5 = '1') then
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-- tmp_bool := FALSE;
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-- end if;
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-- when C =>
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-- tmp_bool := FALSE;
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-- when others =>
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-- null;
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-- end case;
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--
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-- case (input2) is
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-- when C =>
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-- if (input4 = '1') then
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-- tmp_bool := FALSE;
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-- end if;
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-- when others =>
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-- null;
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-- end case;
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--
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-- case (input3) is
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-- when A =>
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-- tmp_bool := FALSE;
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-- when D =>
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-- if (input4 = '0' and input5 = '1') then
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-- tmp_bool := FALSE;
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-- end if;
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-- when others =>
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-- null;
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-- end case;
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--
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-- if (tmp_bool) then
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-- output <= '1';
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-- else
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-- output <= '0';
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-- end if;
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-- end if;
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-- end if;
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-- end process;
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process (all)
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begin
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if rising_edge(clk) then
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if (reset = '1') then
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output <= '0';
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stage <= IN1;
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else
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case (stage) is
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when IN1 =>
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-- DEFAULT
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stage <= IN2;
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case (input1) is
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when A =>
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if (input4 = '1') then
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output <= '0';
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stage <= IN1;
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end if;
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when B =>
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if (input5 = '1') then
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output <= '0';
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stage <= IN1;
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end if;
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when C =>
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output <= '0';
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stage <= IN1;
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when others =>
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null;
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end case;
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when IN2 =>
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-- DEFAULT
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stage <= IN3;
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case (input2) is
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when C =>
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if (input4 = '1') then
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output <= '0';
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stage <= IN1;
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end if;
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when others =>
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null;
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end case;
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when IN3 =>
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-- DEFAULT
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stage <= IN1;
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output <= '1';
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case (input3) is
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when A =>
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output <= '0';
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stage <= IN1;
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when D =>
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if (input4 = '0' and input5 = '1') then
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output <= '0';
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stage <= IN1;
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end if;
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when others =>
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null;
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end case;
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end case;
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end if;
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end if;
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end process;
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end architecture;
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