John Daktylidis
d2c0b37c27
During testing a scenario arose, where a toggling in the last_word signal lane while the rest of the signals were not valid was falsely latched. All entities with "last_word_in" latches were modifies to only latch the signal when in valid state.
37 lines
1.1 KiB
VHDL
37 lines
1.1 KiB
VHDL
-- altera vhdl_input_version vhdl_2008
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-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.rtps_package.all;
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use work.rtps_config_package.all;
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entity key_holder is
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generic (
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LITTLE_ENDIAN : std_logic := '0'
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);
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port (
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-- SYSTEM
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clk : in std_logic;
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reset : in std_logic;
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-- CONTROL
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start : in std_logic;
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opcode : in KEY_HOLDER_OPCODE_TYPE;
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ack : out std_logic;
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decode_error : out std_logic;
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abort : in std_logic;
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-- INPUT
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ready_in : out std_logic;
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valid_in : in std_logic;
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data_in : in std_logic_vector(WORD_WIDTH-1 downto 0);
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last_word_in : in std_logic;
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-- OUTPUT
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ready_out : in std_logic;
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valid_out : out std_logic;
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data_out : out std_logic_vector(WORD_WIDTH-1 downto 0);
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last_word_out : out std_logic
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);
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end entity;
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