greek64/labor-mst
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Add BIAS Configuration

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Greek 2021-03-28 14:11:15 +02:00
parent 8658ac24db
commit 71a6ddcf3b
3 changed files with 7 additions and 6 deletions
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11
src/feedback_loop.vhd
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@ -119,8 +119,7 @@ architecture arch of feedback_loop is
end component; end component;
--*****CONSTANT DECLARATION***** --*****CONSTANT DECLARATION*****
constant CONST_MAX : unsigned(DAC_DATA_WIDTH-1 downto 0) := (others => '1'); constant CONST_BIAS : unsigned(DAC_DATA_WIDTH-1 downto 0) := unsigned(BIAS_OFFSET & "0000");
constant CONST_HALF : unsigned(DAC_DATA_WIDTH-1 downto 0) := (DAC_DATA_WIDTH-1 => '1', others => '0');
constant FACTOR_ONE : unsigned(FACTOR_WIDTH-1 downto 0) := (FACTOR_WIDTH-1 => '1', others => '0'); constant FACTOR_ONE : unsigned(FACTOR_WIDTH-1 downto 0) := (FACTOR_WIDTH-1 => '1', others => '0');
--*****SIGNAL DECLARATION***** --*****SIGNAL DECLARATION*****
@ -251,7 +250,7 @@ begin
) )
port map( port map(
clk => clk, clk => clk,
data_in => (ADC_DATA_WIDTH-1 => '0', others => '1'), data_in => BIAS_OFFSET,
factor => offset_factor1, factor => offset_factor1,
data_out => scaler_offset_1 data_out => scaler_offset_1
); );
@ -299,7 +298,7 @@ begin
) )
port map( port map(
clk => clk, clk => clk,
data_in => (ADC_DATA_WIDTH-1 => '0', others => '1'), data_in => BIAS_OFFSET,
factor => offset_factor2, factor => offset_factor2,
data_out => scaler_offset_2 data_out => scaler_offset_2
); );
@ -358,7 +357,7 @@ begin
-- ADD -- ADD
if (addsub_mode_latch = '1') then if (addsub_mode_latch = '1') then
tmp_res := unsigned("00" & data1_D) + unsigned("00" & data2_D); tmp_res := unsigned("00" & data1_D) + unsigned("00" & data2_D);
tmp_res := tmp_res + ("00" & CONST_HALF); tmp_res := tmp_res + ("00" & CONST_BIAS);
-- Overflow -- Overflow
if (tmp_res(DAC_DATA_WIDTH+1) = '1') then if (tmp_res(DAC_DATA_WIDTH+1) = '1') then
data_out <= (others => '1'); data_out <= (others => '1');
@ -371,7 +370,7 @@ begin
-- SUB -- SUB
else else
tmp_res := unsigned("00" & data1_D) - unsigned("00" & data2_D); tmp_res := unsigned("00" & data1_D) - unsigned("00" & data2_D);
tmp_res := tmp_res + ("00" & CONST_HALF); tmp_res := tmp_res + ("00" & CONST_BIAS);
-- Underflow -- Underflow
if (tmp_res(DAC_DATA_WIDTH+1 downto DAC_DATA_WIDTH) = "11") then if (tmp_res(DAC_DATA_WIDTH+1 downto DAC_DATA_WIDTH) = "11") then
data_out <= (others => '0'); data_out <= (others => '0');

2
src/typedef_package.vhd
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@ -21,6 +21,8 @@ package typedef_package is
constant TIMESTAMP_WIDTH : integer := 32; constant TIMESTAMP_WIDTH : integer := 32;
constant BIAS_OFFSET : std_logic_vector(ADC_DATA_WIDTH-1 downto 0) := (ADC_DATA_WIDTH-1 => '1', others => '0');
--XILLYBUS --XILLYBUS
constant DEBUG_FIFO_DATA_WIDTH : integer := 32; constant DEBUG_FIFO_DATA_WIDTH : integer := 32;
constant DEBUG_FIFO_DEPTH : integer := 16; constant DEBUG_FIFO_DEPTH : integer := 16;