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* Added Zynq 7 documentation

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* Updated sync processes for async reset
* Implemented simple open loop design
	- Added testbench and .do file
This commit is contained in:
Greek 2020-04-01 14:12:04 +02:00
parent 2beb7f4b4d
commit a28aab25fa
7 changed files with 238 additions and 46 deletions
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BIN
doc/ds190-Zynq-7000-Overview.pdf (Stored with Git LFS) Normal file
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doc/ug585-Zynq-7000-TRM.pdf (Stored with Git LFS) Normal file
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35
modelsim/open_loop.do Normal file
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onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /open_loop_tb/clk
add wave -noupdate /open_loop_tb/reset
add wave -noupdate /open_loop_tb/uut/interconnect
add wave -noupdate -divider ADC
add wave -noupdate /open_loop_tb/adc_data_in
add wave -noupdate /open_loop_tb/adc_cs_n
add wave -noupdate /open_loop_tb/uut/adc/stage
add wave -noupdate /open_loop_tb/uut/adc/done
add wave -noupdate -divider DAC
add wave -noupdate /open_loop_tb/uut/dac/buf
add wave -noupdate /open_loop_tb/dac_data_out
add wave -noupdate /open_loop_tb/dac_cs_n
add wave -noupdate /open_loop_tb/dac_ldac
add wave -noupdate /open_loop_tb/uut/dac/stage
add wave -noupdate /open_loop_tb/uut/dac/done
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {966933 ps} 0}
quietly wave cursor active 1
configure wave -namecolwidth 137
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ps
update
WaveRestoreZoom {0 ps} {996596 ps}

97
src/open_loop.vhd Normal file
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity open_loop is
port (
clk : in std_logic;
areset : in std_logic;
adc_data_in : in std_logic;
adc_cs_n : out std_logic;
dac_data_out : out std_logic;
dac_cs_n : out std_logic;
dac_ldac : out std_logic
);
end entity;
architecture arch of open_loop is
--*****SIGNAL DECLARATION*****
signal interconnect : std_logic_vector(15 downto 0) := (others => '0');
signal adc_done : std_logic := '0';
--*****COMPONENT DECLARATION*****
component pmod_ad1_ctrl is
generic(
TRANSFER_CLK_COUNT : integer := 16;
DELAY_CLK_CNT : integer := 2;
DATA_BITS : integer := 12
);
port (
sclk : in std_logic; -- PMOD-AD1
reset : in std_logic;
sdata1 : in std_logic; -- PMOD-AD1
sdata2 : in std_logic; -- PMOD-AD1
enable : in std_logic;
cs_n : out std_logic;-- PMOD-AD1
data1 : out std_logic_vector(DATA_BITS-1 downto 0);
data2 : out std_logic_vector(DATA_BITS-1 downto 0);
done : out std_logic
);
end component;
component pmod_da3_ctrl is
generic(
TRANSFER_CLK_COUNT : integer := 16;
DATA_BITS : integer := 16
);
port (
sclk : in std_logic; -- PMOD-DA3
reset : in std_logic;
start : in std_logic;
data : in std_logic_vector(DATA_BITS-1 downto 0);
cs_n : out std_logic;-- PMOD-DA3
sdata : out std_logic;-- PMOD-DA3
ldac : out std_logic;-- PMOD-DA3
done : out std_logic
);
end component;
begin
--*****COMPONENT INSTANTIATION*****
adc : pmod_ad1_ctrl
generic map(
TRANSFER_CLK_COUNT => 16,
DELAY_CLK_CNT => 2,
DATA_BITS => 12
)
port map(
sclk => clk,
reset => areset,
sdata1 => adc_data_in,
sdata2 => '0',
enable => '1',
cs_n => adc_cs_n,
data1 => interconnect(15 downto 4),
data2 => open,
done => adc_done
);
dac : pmod_da3_ctrl
generic map(
TRANSFER_CLK_COUNT => 16,
DATA_BITS => 16
)
port map(
sclk => clk,
reset => areset,
start => adc_done,
data => interconnect,
cs_n => dac_cs_n,
sdata => dac_data_out,
ldac => dac_ldac,
done => open
);
end architecture;

58
src/open_loop_tb.vhd Normal file
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity open_loop_tb is
end entity;
architecture beh of open_loop_tb is
--*****SIGNAL DECLARATION*****
signal clk, reset, adc_data_in, adc_cs_n, dac_data_out, dac_cs_n, dac_ldac : std_logic := '0';
--*****COMPONENT DECLARATION*****
component open_loop is
port (
clk : in std_logic;
areset : in std_logic;
adc_data_in : in std_logic;
adc_cs_n : out std_logic;
dac_data_out : out std_logic;
dac_cs_n : out std_logic;
dac_ldac : out std_logic
);
end component;
begin
--*****COMPONENT INSTANTIATION*****
uut : open_loop
port map(
clk => clk,
areset => reset,
adc_data_in => '1',
adc_cs_n => adc_cs_n,
dac_data_out => dac_data_out,
dac_cs_n => dac_cs_n,
dac_ldac => dac_ldac
);
clk_prc : process
begin
clk <= '1';
wait for 25 ns;
clk <= '0';
wait for 25 ns;
end process;
process
begin
--INITIALISE SIGNALS
reset <= '1';
wait until rising_edge(clk);
wait until rising_edge(clk);
reset <= '0';
wait;
end process;
end architecture;

48
src/pmod_ad1_ctrl.vhd
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@ -91,32 +91,30 @@ begin
end case;
end process;
sync : process(sclk)
sync : process(sclk, reset)
begin
if (rising_edge(sclk)) then
if (reset = '1') then
-- Internal Signals
buf1 <= (others => '0');
buf2 <= (others => '0');
stage <= IDLE;
count <= 0;
-- Output Signals
cs_n <= '1';
data1 <= (others => '0');
data2 <= (others => '0');
done <= '0';
else
-- Internal Signals
buf1 <= buf1_next;
buf2 <= buf2_next;
stage <= stage_next;
count <= count_next;
-- Output Signals
cs_n <= cs_n_next;
data1 <= buf1_next;
data2 <= buf2_next;
done <= done_next;
end if;
if (reset = '1') then
-- Internal Signals
buf1 <= (others => '0');
buf2 <= (others => '0');
stage <= IDLE;
count <= 0;
-- Output Signals
cs_n <= '1';
data1 <= (others => '0');
data2 <= (others => '0');
done <= '0';
elsif (rising_edge(sclk)) then
-- Internal Signals
buf1 <= buf1_next;
buf2 <= buf2_next;
stage <= stage_next;
count <= count_next;
-- Output Signals
cs_n <= cs_n_next;
data1 <= buf1_next;
data2 <= buf2_next;
done <= done_next;
end if;
end process;

40
src/pmod_da3_ctrl.vhd
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@ -81,28 +81,26 @@ begin
end case;
end process;
sync : process(sclk)
sync : process(sclk, reset)
begin
if (rising_edge(sclk)) then
if (reset = '1') then
-- Internal Signals
buf <= (others => '0');
stage <= IDLE;
count <= 0;
-- Output Signals
cs_n <= '1';
sdata <= '0';
done <= '0';
else
-- Internal Signals
buf <= buf_next;
stage <= stage_next;
count <= count_next;
-- Output Signals
cs_n <= cs_n_next;
sdata <= sdata_next;
done <= done_next;
end if;
if (reset = '1') then
-- Internal Signals
buf <= (others => '0');
stage <= IDLE;
count <= 0;
-- Output Signals
cs_n <= '1';
sdata <= '0';
done <= '0';
elsif (rising_edge(sclk)) then
-- Internal Signals
buf <= buf_next;
stage <= stage_next;
count <= count_next;
-- Output Signals
cs_n <= cs_n_next;
sdata <= sdata_next;
done <= done_next;
end if;
end process;