a28aab25fa
* Updated sync processes for async reset * Implemented simple open loop design - Added testbench and .do file
58 lines
1.4 KiB
VHDL
58 lines
1.4 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity open_loop_tb is
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end entity;
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architecture beh of open_loop_tb is
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--*****SIGNAL DECLARATION*****
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signal clk, reset, adc_data_in, adc_cs_n, dac_data_out, dac_cs_n, dac_ldac : std_logic := '0';
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--*****COMPONENT DECLARATION*****
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component open_loop is
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port (
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clk : in std_logic;
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areset : in std_logic;
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adc_data_in : in std_logic;
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adc_cs_n : out std_logic;
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dac_data_out : out std_logic;
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dac_cs_n : out std_logic;
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dac_ldac : out std_logic
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);
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end component;
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begin
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--*****COMPONENT INSTANTIATION*****
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uut : open_loop
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port map(
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clk => clk,
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areset => reset,
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adc_data_in => '1',
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adc_cs_n => adc_cs_n,
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dac_data_out => dac_data_out,
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dac_cs_n => dac_cs_n,
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dac_ldac => dac_ldac
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);
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clk_prc : process
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begin
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clk <= '1';
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wait for 25 ns;
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clk <= '0';
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wait for 25 ns;
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end process;
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process
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begin
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--INITIALISE SIGNALS
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reset <= '1';
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wait until rising_edge(clk);
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wait until rising_edge(clk);
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reset <= '0';
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wait;
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end process;
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end architecture; |