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* Fix xillybus-FPGA data ordering

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* Add file explaining custom mapping
This commit is contained in:
Greek 2020-04-28 15:12:31 +02:00
parent cd49506685
commit ae928c116b
3 changed files with 9 additions and 5 deletions
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6
mapping.txt Normal file
View File

@ -0,0 +1,6 @@
JA4 ext_clk
JA1 sync_pulse [NOTE: If pin is left floating, it will register as a pulse]
SW7 standby
LED7 standy_status
BTNC reset
BTNU reset_debug

4
src/xillybus_link.vhd
View File

@ -113,7 +113,7 @@ begin
rd_clk => fpga_clk,
rd_addr => config_addr,
wr_addr => mem_addr(CONFIG_MEM_ADDR_WIDTH downto 1),
wen => mem_wen and (not mem_addr(0)), -- Only even adresses
wen => mem_wen and (mem_addr(0)), -- Only odd adresses
ren => config_ren,
wr_data => mem_wr_data,
rd_data => config_data(CONFIG_DATA_WIDTH-1 downto CONFIG_MEM_DATA_WIDTH)
@ -129,7 +129,7 @@ begin
rd_clk => fpga_clk,
rd_addr => config_addr,
wr_addr => mem_addr(CONFIG_MEM_ADDR_WIDTH downto 1),
wen => mem_wen and (mem_addr(0)), -- Only odd adresses
wen => mem_wen and (not mem_addr(0)), -- Only even adresses
ren => config_ren,
wr_data => mem_wr_data,
rd_data => config_data(CONFIG_MEM_DATA_WIDTH-1 downto 0)

4
sw/read_debug.c
View File

@ -62,9 +62,7 @@ int main(int argc, char *argv[]){
data = buffer;
printf("\nADC_DATA2_MAX: %u\nADC_DATA1_MAX: %u\nSCALER_MAX: %u\nDAC_MAX: %u\n", data[0], data[1], data[2], data[3]);
/* uint64_t* test = buffer;*/
/* printf("DATA: %llX\n", test[0]);*/
printf("\nADC_DATA1_MAX: %u\nADC_DATA2_MAX: %u\nSCALER_MAX: %u\nDAC_MAX: %u\n", data[0], data[1], data[3], data[2]);
}
//Never Reached