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* Update diagram (No transparency)

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* Fix Markdown table
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Greek 2020-04-29 23:53:49 +02:00
parent 922c7cdb83
commit c638cb7191
2 changed files with 3 additions and 16 deletions
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Readme.md
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@ -29,6 +29,8 @@
# Board Mapping # Board Mapping
Zedboard Pin | Description
--------------------------------|---------------
JC1 PMOD Connector (Upper Row) | PMOD-AD1 Board JC1 PMOD Connector (Upper Row) | PMOD-AD1 Board
JD1 PMOD Connector (Upper Row) | PMOD-DA3 Board JD1 PMOD Connector (Upper Row) | PMOD-DA3 Board
JA1 PMOD JA1 Pin | Optional External Clock [NOTE: Clk has to be connected in VHDl and PLL has to be reconfigured accordingly] JA1 PMOD JA1 Pin | Optional External Clock [NOTE: Clk has to be connected in VHDl and PLL has to be reconfigured accordingly]
@ -100,18 +102,3 @@ Currently the FPGA logic sends every second the max values of the both ADC chann
The `read_debug.c` C program can be used to read the debug values. Since the program enters an endless loop, a signal handler has beeen implemented and the program can be safely terminated with `CTRL-C` and co. The `read_debug.c` C program can be used to read the debug values. Since the program enters an endless loop, a signal handler has beeen implemented and the program can be safely terminated with `CTRL-C` and co.
e.g. `./read_debug /dev/xillybus_debug` e.g. `./read_debug /dev/xillybus_debug`

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