Greek
|
89182e8060
|
* Route sclk for ADC/DAC through controller entity itself
* Remove ADC/DAC input/outputs constraints
* Fix PMOD-AS1 Controller
- Invert SCLK
|
2020-04-29 14:01:01 +02:00 |
|
Greek
|
a5c68d1fea
|
* Add documentation
- Zedboard Rev.D Errata
* Add debug leds to top entity
* Pin mapping
|
2020-04-27 13:41:10 +02:00 |
|
Greek
|
11532daee2
|
* Modify xillinux vivado project
- Remove PS-GPIO
|
2020-04-26 17:53:15 +02:00 |
|
Greek
|
bb07d0a072
|
* Modify xillinux vivado project
- Add custom xillybus IP core to vivado design
- Add feedback_top
TODO: Remove PS_GPIO and connect custom pins
|
2020-04-26 17:36:25 +02:00 |
|
Greek
|
9818d0d27a
|
* Added Xillybus demo project
|
2020-04-26 11:42:06 +02:00 |
|