779cd73e8d
* Made cap of addsub selectable via signal
* Added debug reporting
- MAX ADC Input 1
- MAX ADC Input 2
- MAX Scaler output
- MAX DAC Output
* Added Async FIFO
* Added Simple Dual Port RAM
* Added Feedback Controller
* Added Xillybus Link
* Moved testbenches to seperate directory
108 lines
3.5 KiB
VHDL
108 lines
3.5 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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-- Controller for the PMOD DA3 Digilent Board.
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-- The controller sends the input 'data' word to the DAC when 'start' is asserted. The 'data' input has
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-- to be valid only during the period 'start' is asserted, as for the transfer the word is latched
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-- internally. When the transfer is done, the 'done' signal is asserted for one clock cycle. The 'start'
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-- and 'done' cycle can be high at the same time, allowing the done signal to be asynchronously connected
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-- to the 'start' signal to save on latency.
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entity pmod_da3_ctrl is
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generic(
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TRANSFER_CLK_COUNT : integer := 16;
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DATA_WIDTH : integer := 16
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);
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port (
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sclk : in std_logic; -- PMOD-DA3
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reset : in std_logic;
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start : in std_logic;
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data : in std_logic_vector(DATA_WIDTH-1 downto 0);
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cs_n : out std_logic;-- PMOD-DA3
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sdata : out std_logic;-- PMOD-DA3
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ldac : out std_logic;-- PMOD-DA3
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done : out std_logic
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);
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end entity;
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architecture arch of pmod_da3_ctrl is
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--*****TYPE DECLARATION*****
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type STAGE_TYPE is (IDLE, TRANSFER);
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--*****SIGNAL DECLARATIONS*****
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signal buf, buf_next : std_logic_vector(DATA_WIDTH-1 downto 0) := (others => '0');
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signal stage, stage_next : STAGE_TYPE := IDLE;
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signal count, count_next : integer range 0 to TRANSFER_CLK_COUNT := 0;
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-- Output Signals
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signal cs_n_next : std_logic := '1';
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signal sdata_next : std_logic := '0';
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signal done_next : std_logic := '0';
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begin
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--LDAC Hardwired to ground
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ldac <= '0';
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state : process(all)
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begin
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-- DEFAULT VALUES
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buf_next <= buf;
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stage_next <= stage;
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count_next <= count;
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done_next <= '0';
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cs_n_next <= '1';
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sdata_next <= '0';
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case stage is
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when IDLE =>
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if (start = '1') then
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stage_next <= TRANSFER;
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cs_n_next <= '0';
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count_next <= 1;
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-- Shift first bit into DAC
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buf_next <= data(DATA_WIDTH-2 downto 0) & '0';
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sdata_next <= data(DATA_WIDTH-1);
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end if;
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when TRANSFER =>
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-- Shift Bits into DAC
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buf_next <= buf(DATA_WIDTH-2 downto 0) & '0';
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sdata_next <= buf(DATA_WIDTH-1);
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cs_n_next <= '0';
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if (count = TRANSFER_CLK_COUNT) then
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cs_n_next <= '1';
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stage_next <= IDLE;
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done_next <= '1';
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else
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count_next <= count + 1;
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end if;
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end case;
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end process;
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sync : process(sclk, reset)
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begin
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if (reset = '1') then
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-- Internal Signals
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buf <= (others => '0');
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stage <= IDLE;
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count <= 0;
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-- Output Signals
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cs_n <= '1';
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sdata <= '0';
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done <= '0';
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elsif (rising_edge(sclk)) then
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-- Internal Signals
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buf <= buf_next;
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stage <= stage_next;
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count <= count_next;
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-- Output Signals
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cs_n <= cs_n_next;
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sdata <= sdata_next;
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done <= done_next;
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end if;
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end process;
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end architecture;
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