3 Commits

Author	SHA1	Message	Date
Greek	779cd73e8d	* Moved config/constants to central package ... * Made cap of addsub selectable via signal * Added debug reporting - MAX ADC Input 1 - MAX ADC Input 2 - MAX Scaler output - MAX DAC Output * Added Async FIFO * Added Simple Dual Port RAM * Added Feedback Controller * Added Xillybus Link * Moved testbenches to seperate directory	2020-04-26 11:35:46 +02:00
Greek	a28aab25fa	* Added Zynq 7 documentation ... * Updated sync processes for async reset * Implemented simple open loop design - Added testbench and .do file	2020-04-01 14:12:04 +02:00
Greek	2beb7f4b4d	* .gitignore update ... * Added implementation for PMOD-AD1 Controller including testbench * Added implementation for PMOD-DA3 Controller including testbench	2020-03-12 20:20:35 +01:00