labor-mst/xillinux-syn/vhdl
Greek bb07d0a072 * Modify xillinux vivado project
- Add custom xillybus IP core to vivado design
	- Add feedback_top
TODO: Remove PS_GPIO and connect custom pins
2020-04-26 17:36:25 +02:00
..
src * Modify xillinux vivado project 2020-04-26 17:36:25 +02:00
xillydemo-vivado.tcl * Added Xillybus demo project 2020-04-26 11:42:06 +02:00
xillydemo.xise * Added Xillybus demo project 2020-04-26 11:42:06 +02:00