Change Type-Dependant Code Interface, and Code refactoring
The instantiation of the KEY related entities is moved outside the DDS Endpoints (Currently only changed in DDS Writer). Define new KEY_HOLDER entity that is responsible for all Key related type-specific code. Fix syntax of DDS Writer, and misc code refactoring.
This commit is contained in:
parent
3ba5fae871
commit
981ca09149
15
src/TODO.txt
15
src/TODO.txt
@ -267,6 +267,21 @@ DESIGN DECISIONS
|
||||
requested until reception). This means that during the ACKNACK response delay, we can just parse
|
||||
the new request bitmap and overwrite the last old one.
|
||||
|
||||
* Since all code related to encoding/decoding the DATA stream is dependent on the IDL type
|
||||
specification, we have to encapsule that code separately and link them as necessary. Two such
|
||||
dynamic Entities are defined: KEY_HOLDER, and <TYPENAME>_WRAPPER.
|
||||
The KEY_HOLDER Entity contains a Byte-Wide internal memory (In size equal to the maximum key size),
|
||||
that can be filled with both PLAIN_CDR/PL_CDR DATA Streams, and PLAIN_CDR/PL_CDR Serialized Key
|
||||
Streams. The Entity allows outputting the memory contents (Key) either in a KEY_HASH format (needs
|
||||
to instantiate a MD5 calculator), or in Serialized Key Format. The Entity uses the start/opcode/ack
|
||||
interface for operations (similar to the RTPS/DDS Interface).
|
||||
The <TYPENAME>_WRAPPER entity has all type-components linked to ports and latched in registers. In
|
||||
output mode the entity is able to fill the registers with a PLAIN_CDR/PL_CDR Data Stream, and in
|
||||
input mode the registers are filled directly from the input ports and the Entity is able to produce
|
||||
a PLAIN_CDR/PL_CDR Data Stream from the registers.
|
||||
Due to the type-specific nature of the entities, those are not instantiated inside the DDS Endpoints,
|
||||
but will be instantiated in a wrapper and linked through port mapping with the DDS Enspoints.
|
||||
|
||||
PROTOCOL UNCOMPLIANCE
|
||||
=====================
|
||||
* Partition QoS
|
||||
|
||||
@ -101,7 +101,7 @@ begin
|
||||
full_rtps => '0',
|
||||
last_word_out_rtps => open,
|
||||
data_out_rtps => open,
|
||||
assert_liveliness => '0',
|
||||
liveliness_assertion => '0',
|
||||
data_available => '0',
|
||||
start_hc => start_hc,
|
||||
opcode_hc => open,
|
||||
|
||||
@ -101,7 +101,7 @@ begin
|
||||
full_rtps => '0',
|
||||
last_word_out_rtps => open,
|
||||
data_out_rtps => open,
|
||||
assert_liveliness => '0',
|
||||
liveliness_assertion => '0',
|
||||
data_available => '0',
|
||||
start_hc => start_hc,
|
||||
opcode_hc => open,
|
||||
|
||||
@ -85,7 +85,7 @@ begin
|
||||
full_rtps => '0',
|
||||
last_word_out_rtps => open,
|
||||
data_out_rtps => open,
|
||||
assert_liveliness => '0',
|
||||
liveliness_assertion => '0',
|
||||
data_available => '0',
|
||||
start_hc => start_hc,
|
||||
opcode_hc => open,
|
||||
|
||||
@ -108,7 +108,7 @@ begin
|
||||
full_rtps => fifo_full,
|
||||
last_word_out_rtps => fifo_in(WORD_WIDTH),
|
||||
data_out_rtps => fifo_in(WORD_WIDTH-1 downto 0),
|
||||
assert_liveliness => '0',
|
||||
liveliness_assertion => '0',
|
||||
data_available => data_available,
|
||||
start_hc => start_hc,
|
||||
opcode_hc => opcode_hc,
|
||||
|
||||
@ -108,7 +108,7 @@ begin
|
||||
full_rtps => fifo_full,
|
||||
last_word_out_rtps => fifo_in(WORD_WIDTH),
|
||||
data_out_rtps => fifo_in(WORD_WIDTH-1 downto 0),
|
||||
assert_liveliness => '0',
|
||||
liveliness_assertion => '0',
|
||||
data_available => data_available,
|
||||
start_hc => start_hc,
|
||||
opcode_hc => opcode_hc,
|
||||
|
||||
@ -108,7 +108,7 @@ begin
|
||||
full_rtps => fifo_full,
|
||||
last_word_out_rtps => fifo_in(WORD_WIDTH),
|
||||
data_out_rtps => fifo_in(WORD_WIDTH-1 downto 0),
|
||||
assert_liveliness => '0',
|
||||
liveliness_assertion => '0',
|
||||
data_available => data_available,
|
||||
start_hc => start_hc,
|
||||
opcode_hc => opcode_hc,
|
||||
|
||||
@ -108,7 +108,7 @@ begin
|
||||
full_rtps => fifo_full,
|
||||
last_word_out_rtps => fifo_in(WORD_WIDTH),
|
||||
data_out_rtps => fifo_in(WORD_WIDTH-1 downto 0),
|
||||
assert_liveliness => '0',
|
||||
liveliness_assertion => '0',
|
||||
data_available => data_available,
|
||||
start_hc => start_hc,
|
||||
opcode_hc => opcode_hc,
|
||||
|
||||
@ -108,7 +108,7 @@ begin
|
||||
full_rtps => fifo_full,
|
||||
last_word_out_rtps => fifo_in(WORD_WIDTH),
|
||||
data_out_rtps => fifo_in(WORD_WIDTH-1 downto 0),
|
||||
assert_liveliness => '0',
|
||||
liveliness_assertion => '0',
|
||||
data_available => data_available,
|
||||
start_hc => start_hc,
|
||||
opcode_hc => opcode_hc,
|
||||
|
||||
@ -108,7 +108,7 @@ begin
|
||||
full_rtps => fifo_full,
|
||||
last_word_out_rtps => fifo_in(WORD_WIDTH),
|
||||
data_out_rtps => fifo_in(WORD_WIDTH-1 downto 0),
|
||||
assert_liveliness => '0',
|
||||
liveliness_assertion => '0',
|
||||
data_available => data_available,
|
||||
start_hc => start_hc,
|
||||
opcode_hc => opcode_hc,
|
||||
|
||||
@ -108,7 +108,7 @@ begin
|
||||
full_rtps => fifo_full,
|
||||
last_word_out_rtps => fifo_in(WORD_WIDTH),
|
||||
data_out_rtps => fifo_in(WORD_WIDTH-1 downto 0),
|
||||
assert_liveliness => '0',
|
||||
liveliness_assertion => '0',
|
||||
data_available => data_available,
|
||||
start_hc => start_hc,
|
||||
opcode_hc => opcode_hc,
|
||||
|
||||
@ -108,7 +108,7 @@ begin
|
||||
full_rtps => fifo_full,
|
||||
last_word_out_rtps => fifo_in(WORD_WIDTH),
|
||||
data_out_rtps => fifo_in(WORD_WIDTH-1 downto 0),
|
||||
assert_liveliness => '0',
|
||||
liveliness_assertion => '0',
|
||||
data_available => data_available,
|
||||
start_hc => start_hc,
|
||||
opcode_hc => opcode_hc,
|
||||
|
||||
@ -34,7 +34,7 @@ architecture testbench of L1_rtps_writer_test2_vrkdn is
|
||||
signal clk, empty_user, empty_meta, rd_meta, last_word_in_meta, last_word_in_hc, last_word_out_rtps : std_logic := '0';
|
||||
signal reset : std_logic := '1';
|
||||
signal data_in_meta, data_out, data_in_hc : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
|
||||
signal wr_sig, full, data_available, assert_liveliness : std_logic := '0';
|
||||
signal wr_sig, full, data_available, liveliness_assertion : std_logic := '0';
|
||||
signal ready_in_hc, valid_in_hc, ack_hc, done_hc, get_data_hc, start_hc : std_logic := '0';
|
||||
signal seq_nr_hc : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN;
|
||||
signal stim_stage_meta : SEND_STAGE_TYPE := IDLE;
|
||||
@ -107,7 +107,7 @@ begin
|
||||
full_rtps => fifo_full,
|
||||
last_word_out_rtps => fifo_in(WORD_WIDTH),
|
||||
data_out_rtps => fifo_in(WORD_WIDTH-1 downto 0),
|
||||
assert_liveliness => assert_liveliness,
|
||||
liveliness_assertion => liveliness_assertion,
|
||||
data_available => data_available,
|
||||
start_hc => start_hc,
|
||||
opcode_hc => opcode_hc,
|
||||
@ -248,7 +248,7 @@ begin
|
||||
end if;
|
||||
end procedure;
|
||||
|
||||
procedure push_hb(endpoint : in ENDPOINT_DATA_TYPE; first : in SEQUENCENUMBER_TYPE; last : in SEQUENCENUMBER_TYPE; assert_liveliness : in boolean) is
|
||||
procedure push_hb(endpoint : in ENDPOINT_DATA_TYPE; first : in SEQUENCENUMBER_TYPE; last : in SEQUENCENUMBER_TYPE; liveliness_assertion : in boolean) is
|
||||
begin
|
||||
reference := EMPTY_TEST_PACKET;
|
||||
-- OUTPUT HEADER
|
||||
@ -266,7 +266,7 @@ begin
|
||||
sub.readerId := ENTITYID_UNKNOWN;
|
||||
sub.firstSN := first;
|
||||
sub.lastSN := last;
|
||||
sub.flags(SUBMESSAGE_LIVELINESS_FLAG_POS) := '1' when (assert_liveliness) else '0';
|
||||
sub.flags(SUBMESSAGE_LIVELINESS_FLAG_POS) := '1' when (liveliness_assertion) else '0';
|
||||
sub.count := std_logic_vector(to_unsigned(count, CDR_LONG_WIDTH));
|
||||
gen_rtps_submessage(sub, reference);
|
||||
fix_output_packet(reference);
|
||||
@ -335,7 +335,7 @@ begin
|
||||
new_cc <= '0';
|
||||
stim_done <= '0';
|
||||
start_meta <= '0';
|
||||
assert_liveliness <= '0';
|
||||
liveliness_assertion <= '0';
|
||||
reset <= '1';
|
||||
wait until rising_edge(clk);
|
||||
wait until rising_edge(clk);
|
||||
@ -399,10 +399,10 @@ begin
|
||||
test_cc(2).payload <= gen_payload;
|
||||
test_cc_fill <= 3;
|
||||
new_cc <= '1';
|
||||
assert_liveliness <= '1';
|
||||
liveliness_assertion <= '1';
|
||||
wait until rising_edge(clk);
|
||||
new_cc <= '0';
|
||||
assert_liveliness <= '0';
|
||||
liveliness_assertion <= '0';
|
||||
wait until rising_edge(clk);
|
||||
|
||||
Log("Send HEARTBEAT to Endpoint 0,1 [Liveliness Flag]", INFO);
|
||||
@ -511,9 +511,9 @@ begin
|
||||
wait_on_idle;
|
||||
|
||||
Log("Assert Liveliness", INFO);
|
||||
assert_liveliness <= '1';
|
||||
liveliness_assertion <= '1';
|
||||
wait until rising_edge(clk);
|
||||
assert_liveliness <= '0';
|
||||
liveliness_assertion <= '0';
|
||||
wait until rising_edge(clk);
|
||||
|
||||
Log("Send HEARTBEAT to Endpoint 0,1,2,3,4", INFO);
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -120,18 +120,7 @@ begin
|
||||
if (key_gen_valid_out) then
|
||||
cnt_next <= cnt + 1;
|
||||
|
||||
case (cnt) is
|
||||
when 0 =>
|
||||
key_hash_next(0) <= key_gen_data_out;
|
||||
when 1 =>
|
||||
key_hash_next(1) <= key_gen_data_out;
|
||||
when 2 =>
|
||||
key_hash_next(2) <= key_gen_data_out;
|
||||
when 3 =>
|
||||
key_hash_next(3) <= key_gen_data_out;
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
key_hash_next(cnt) <= key_gen_data_out;
|
||||
|
||||
if (key_gen_last_word_out = '1') then
|
||||
stage_next <= FINISHED_KEY_HASH;
|
||||
@ -143,21 +132,13 @@ begin
|
||||
if (ready_out = '1') then
|
||||
cnt_next <= cnt + 1;
|
||||
|
||||
case (cnt) is
|
||||
when 0 =>
|
||||
data_out <= key_hash(0);
|
||||
when 1 =>
|
||||
data_out <= key_hash(1);
|
||||
when 2 =>
|
||||
data_out <= key_hash(2);
|
||||
when 3 =>
|
||||
data_out <= key_hash(3);
|
||||
last_word_out <= '1';
|
||||
data_out <= key_hash(cnt);
|
||||
|
||||
if (cnt = key_hash'length-1) then
|
||||
last_word_out <= '1';
|
||||
-- DONE
|
||||
stage_next <= IDLE;
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
when others =>
|
||||
null;
|
||||
|
||||
24
src/key_holder.vhd
Normal file
24
src/key_holder.vhd
Normal file
@ -0,0 +1,24 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity key_holder is
|
||||
port (
|
||||
clk : in std_logic;
|
||||
reset : in std_logic;
|
||||
|
||||
start : in std_logic;
|
||||
opcode : in KEY_HOLDER_TYPE;
|
||||
ack : in std_logic;
|
||||
|
||||
data_in : in std_logic_vector(WORD_WIDTH-1 downto 0);
|
||||
valid_in : in std_logic;
|
||||
ready_in : out std_logic;
|
||||
last_word_in : in std_logic;
|
||||
|
||||
data_out : out std_logic_vector(WORD_WIDTH-1 downto 0);
|
||||
valid_out : out std_logic;
|
||||
ready_out : in std_logic;
|
||||
last_word_out : out std_logic
|
||||
);
|
||||
end entity;
|
||||
@ -42,8 +42,10 @@ package rtps_config_package is
|
||||
constant OPCODE_LIVELINESS_UPDATE : std_logic_vector(ENDPOINT_MATCH_OPCODE_WIDTH-1 downto 0) := x"55000003";
|
||||
|
||||
type HISTORY_CACHE_OPCODE_TYPE is (NOP, ADD_CACHE_CHANGE, GET_CACHE_CHANGE, ACK_CACHE_CHANGE, NACK_CACHE_CHANGE, REMOVE_CACHE_CHANGE, REMOVE_WRITER, GET_MIN_SN, GET_MAX_SN);
|
||||
type KEY_HOLDER_TYPE is (NOP, PUSH_DATA, PUSH_SERIALIZED_KEY, READ_KEY_HASH, READ_SERIALIZED_KEY);
|
||||
type KEY_GENERATOR_OPCODE_TYPE is (NOP, WRITE_PAYLOAD, READ_KEY, READ_SIZE);
|
||||
type HISTORY_CACHE_RESPONSE_TYPE is (OK, REJECTED, INVALID, ERROR);
|
||||
type DDS_WRITER_OPCODE_TYPE is (NOP, REGISTER_INSTANCE, WRITE, DISPOSE, UNREGISTER_INSTANCE, LOOKUP_INSTANCE, WAIT_FOR_ACKNOWLEDGEMENTS, GET_OFFERED_DEADLINE_MISSED_STATUS, ASSERT_LIVELINESS, GET_LIVELINESS_LOST_STATUS);
|
||||
|
||||
-- Sample Status Info Flags
|
||||
constant SSI_DISPOSED_FLAG : natural := STATUS_INFO_DISPOSED_FLAG;
|
||||
|
||||
@ -1742,6 +1742,14 @@ begin
|
||||
mem_pos_next <= 0;
|
||||
mem_stage_next <= FIND_EMPTY_SLOT;
|
||||
mem_cnt_next <= 0;
|
||||
-- Set Endpoint Data
|
||||
mem_endpoint_data_next <= ZERO_ENDPOINT_DATA;
|
||||
mem_endpoint_data_next.guid <= guid_next;
|
||||
mem_endpoint_data_next.addr <= addr_next;
|
||||
mem_endpoint_data_next.portn <= portn_next;
|
||||
mem_endpoint_data_next.next_seq_nr <= SEQUENCENUMBER_UNKNOWN when (DURABILITY_QOS = VOLATILE_DURABILITY_QOS) else FIRST_SEQUENCENUMBER;
|
||||
mem_endpoint_data_next.lease_deadline <= lease_deadline;
|
||||
mem_endpoint_data_next.res_time <= TIME_INVALID;
|
||||
when UPDATE_ENDPOINT =>
|
||||
mem_stage_next <= UPDATE_ENDPOINT;
|
||||
if (RELIABILTY_QOS = RELIABLE_RELIABILITY_QOS and check_mask(mem_field_flags,EMF_IPV4_ADDR_FLAG)) then
|
||||
|
||||
@ -48,7 +48,7 @@ entity rtps_writer is
|
||||
last_word_out_rtps : out std_logic;
|
||||
data_out_rtps : out std_logic_vector(WORD_WIDTH-1 downto 0);
|
||||
-- FROM HC
|
||||
assert_liveliness : in std_logic;
|
||||
liveliness_assertion : in std_logic;
|
||||
data_available : in std_logic;
|
||||
start_hc : out std_logic;
|
||||
opcode_hc : out HISTORY_CACHE_OPCODE_TYPE;
|
||||
@ -467,7 +467,7 @@ begin
|
||||
data_out_rtps <= (others => '0');
|
||||
|
||||
-- Assert Liveliness Latch Setter
|
||||
if (assert_liveliness = '1') then
|
||||
if (liveliness_assertion = '1') then
|
||||
assert_liveliness_latch_next <= '1';
|
||||
end if;
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user