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Make Templates for reader/writer wrapper and key_holder

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Templates with the pre-defined code hull for the reader_wrapper,
writer_wrapper, and key_holder were created.
A "cookbook" of how to expand this TEMPLATES to create type specific IDL
conversions was also added.
The "code generation" is kept general to allow a code generator to
automatically produce this wrappers in the future.
This commit is contained in:
Greek 2021-11-08 17:10:43 +01:00
parent d907a85c07
commit af1de8bab8
15 changed files with 1773 additions and 212 deletions
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READER_WRAPPER
##############
GENERAL
=======
In encoding version 1 all topic types marked with extensibility of FINAL or APPENDABLE are using the
PLAIN_CDR encoding. On the other hand types marked with extensibility MUTABLE are encoded in PL_CDR.[1]
The members of the topic type are handled in declaration order, each in it's own 'decode_stage'.
The 'GET_PAYLOAD_HEADER' stage jumps to the stage handling the first declared member in the topic type.
Each stage jumps to the decode_stage of the next declared member.
If there is no next declared member, stage 'SKIP_PAYLOAD' is selected.
The signal 'align_offset' keeps track of the current alignement offset (Basically byte_count mod 8).
The general procedure is that the input is latched ('data_in_latch') allowing to work Byte-oriented, since
the input is word-sized. Each time the 'align_offset' reaches "x11" a new input word is latched.
The CDR Encodings of all types are Byte aligned.
PRIMITIVES TYPES
================
Primitive Types are directly latched into registers of equal size (name <TYPENAME>_lach), that are
accesible directly via a port of the same name (i.e. <TYPENAME>).
The name of the generated decode_stage is GET_<TYPENAME>.
The generated decode_stage first checks the alignement and aligns the stream using the 'ALIGN_STREAM' stage.
* Primitive size 1
The input is directly latched using the get_sub_vector function together with the current 'align_offset',
1 is added to the 'align_offset', the decode_stage of the next declared member is taken, and the 'FETCH'
stage is called if the current 'align_offset' is "x11".
* Primitive size 2
The input is directly latched using the get_sub_vector function together with the current 'align_offset',
2 is added to the 'align_offset', the decode_stage of the next declared member is taken, and the 'FETCH'
stage is called if the current 'align_offset' is "x1x".
* Primitive size 4
The input is directly latched, 4 is added to the 'align_offset', the decode_stage of the next declared
member is taken, and the 'FETCH' stage is called.
* Primitive size 8
The decode_stage is divided with the help of 'cnt' in 3 sub-stages. A helper double-word latch 'dw_latch'
is used. The first 2 sub-stages latch the word into the helper latch (calling 'FETCH' stage each time),
and the last sub-stage is for latching the final signal in it's final place. In the last sub-stage 8 is
added to the 'align_offset' and the decode_stage of the next declared member is taken.
NOTE: The extra sub-stage is used to push the signal to a memory in a single operation
* Primitive size 16
The decode_stage is divided with the help of 'cnt' in 5 sub-stages. A helper quad-word latch 'qw_latch'
is used. The first 4 sub-stages latch the word into the helper latch (calling 'FETCH' stage each time),
and the last sub-stage is for latching the final signal in it's final place. In the last sub-stage 16 is
added to the 'align_offset' and the decode_stage of the next declared member is taken.
NOTE: The extra sub-stage is used to push the signal to a memory in a single operation
The alignements and sizes for IDL primitive types are following:
IDL TYPE SIZE ALIGNMENT [2]
int8/uint8 1 1
octet 1 1
boolean 1 1
char 1 1
short/unsigned short 2 2
wchar 2 2
long/unsigned long 4 4
float 4 4
long long/unsigned long long 8 8
double 8 8
long double 16 8
ENUMERATED TYPES
================
Enumerations and Bitmasks are encoded into primitives according to their bit_bound.
The width of the latch and port is the same as the specified bit_bound, but the CDR encoding is always
Byte-aligned, so care as to be taken (i.e. resizing).
Other than that the same rules as for primitives apply.
BIT_BOUND PRIMITIVE [3]
1-8 octet
9-16 short
17-32 long (DEFAULT if no bit_bound specified)
33-64 long long
COLLECTION TYPES
================
In contrast to primitive types, collection types are latched into memories of equal width and depth
equal to the maximum length. Memory access port signals are made available to the user to allow to access
the contents.
SEQUENCE
--------
The name of the generated memory is <TYPENAME>_mem, and the memory signals are connected via signals of
name <TYPENAME>_mem_<SIGNALNAME>. The generated memory uses a MAX_BURST_LENGTH of 1.
Following Port signals are defined:
NAME DIRECTION CONNECTED
<TYPENAME>_len out <TYPENAME>_len_latch
<TYPENAME>_addr in <TYPENAME>_mem_addr in 'IDLE' stage
<TYPENAME>_ready out <TYPENAME>_mem_ready_in in 'IDLE' stage, else '0' [NOTE: ANDing for aggregated elment types (see Structures below)]
<TYPENAME>_ren in <TYPENAME>_mem_read and <TYPENAME>_mem_valid_in in 'IDLE' stage
<TYPENAME>_valid out <TYPENAME>_mem_valid_out [NOTE: ANDing for aggregated elment types (see Structures below)]
<TYPENAME>_ack in <TYPENAME>_mem_ready_out in 'IDLE' stage
<TYPENAME> out <TYPENAME>_mem_data_out
2 decode_stages are defined:
* GET_<TYPENAME>_LENGTH
The first decode_stage is similar to a 4-byte primitive decode stage and latches the length of the
sequence into the <TYPENAME>_len_latch. If the length is equal zero, the decode_stage of the next
declared member is taken, instead of the GET_<TYPENAME>. A special <TYPENAME>_cnt counter (used to
index the type specific memory) is initialized to 0.
* GET_<TYPENAME>
This stage is similar to the respective primitive decode_stage with following valiations:
The <TYPENAME>_cnt is used to set the current <TYPENAME>_mem_addr. On sucessful latch
(<TYPENAME>_mem_valid_in and <TYPENAME>_ready_in = '1') the align_offset is incremented by the
respective size, the <TYPENAME>_cnt is incremented, and if the current <TYPENAME>_cnt is equal to
<TYPENAME>_len-1, the decode_stage of the next declared member is taken.
ARRAY
-----
Array is similar to the sequence, but has no length encoding (since it always has the smae size).
That means that there is no <TYPENAME>_len port signal, <TYPENAME>_len_latch latch, and also no
GET_<TYPENAME>_LENGTH stage.
The initialization of the <TYPENAME>_cnt has to be done in the previous decode_stage.
The <TYPENAME>_cnt is compared against the fixed array length consatnt form the type package.
MAP
---
Maps are basically sequences of aggregated element type [4]:
struct <TYPENAME>_Entry {
<key_type> key;
<value_type> value;
};
sequence<<TYPENAME>_Entry> <TYPENAME>;
For simplicity the name of the structure is ignored.
(I.e. the generated names are <TYPENAME>_key, <TYPENAME>_value instead of
<TYPENAME>_<TYPENAME>_Entry_key and <TYPENAME>_<TYPENAME>_Entry_value)
AGGREGATED TYPES
================
STRUCTURE
---------
If a type member is in itself another structure, the generated <TYPENAME> ports,signals,memories.stages,etc
are split into <TYPENAME>_<SUB-TYPENAME> signals,ports,memories,stages,etc.
In case the element type of a collection type is an aggregated type, a new decode_stage called
<TYPENAME>_MEMBER_END is generated, which handles the <TYPENAME>_cnt increment and check which
normally be handled in the GET_<TYPENAME> decode_stage. The <TYPENAME>_ready and <TYPENAME>_valid
port signals are generated by ANDing the respective memory signals of all sub-elements.
UNION
-----
Due to the dynamic nature of unions, all defined sub-types have to be handled equally.
Similar to structures the generated <TYPENAME> objects are split into <TYPENAME>_<SUB-TYPENAME> objects,
including the special <TYPENAME>_d objects, which handle the value of the discriminator itself.
In contrast to structures, the first decode_stage (GET_<TYPENAME>_D) selects the next decode_stage
according to the discriminator value itself. The rest of the generated decode_stages select the
decode_stage of the next declared member.
NESTED COLLECTIONS
==================
If a collection type has in itself another collection type, an array of memories is generated, and the
respective memory connection signals are also multidimensional (Meaning that custom types have to be
created).
The <OUTER_COLLECTION_TYPENAME>_cnt of the outer collection is used to index the multidimensional signals
of the inner collection.
The <OUTER_COLLECTION_TYPENAME>_ready and <OUTER_COLLECTION_TYPENAME>_valid ports of the outer collection
are no longer dependant on the inner collection (If the outer array has no other elements type except the
inner collection the ports have to be hardwired).
A new <OUTER_COLLECTION_TYPENAME>_addr_latch helper latch is defined, that latches the
<OUTER_COLLECTION_TYPENAME>_addr port when the <OUTER_COLLECTION_TYPENAME>_<INNER_COLLECTION_TYPENAME>_ren
port signal is '1'. This address latch is used to connect the correct memory to the
<OUTER_COLLECTION_TYPENAME>_<INNER_COLLECTION_TYPENAME> and
<OUTER_COLLECTION_TYPENAME>_<INNER_COLLECTION_TYPENAME>_valid port signals.
OPTIONALS
=========
If a type member is specified as optional, a special header is preceding the CDR encoding.[5]
Generally the same procedure as the type of the optional member is followed with following
modifications.
A new <TYPENAME>_opt port signal is defined, that is connected to a <TYPENAME>_opt_latch latch.
The previous decode_stage selects the 'GET_OPTIONAL_HEADER' decode_stage, and sets the 'return_stage'
to the actual next decode_stage (The decode_stage of the optional member).
The first generated decode_stage of the <TYPENAME> (i.e. the stage that was in return_stage) checks
the 'optional' signal before anything else (even before the alignement). If 'optional' is '0', it sets
the <TYPENAME>_opt_latch to '0' and selects the decode_stage of the next declared member. Otherwise
the <TYPENAME>_opt_latch is set to '1'.
WRITER_WRAPPER
##############
GENERAL
=======
In General the writer_wrapper is a similar layout to the reader_wrapper with following modifications.
All "GET_*" stages are renamed to "WRITE_*".
The "FETCH" stage is renamed to "PUSH".
'write_sub_vector' is used to write into 'data_out_latch' (instead of 'get_sub_vector' and 'data_in_latch').
The direction of the <TYPENAME> port signals are inverted (i.e. in).
Instead of calling 'SKIP_PAYLOAD' stage on the last declared member, the 'PUSH' stage is explicitly called
and the 'encode_done' and 'finalize_payload' signals are set.
COLLECTION TYPE
===============
The port signals of all collection types are modified as follows:
MOD NAME DIRECTION CONNECTED
remove <TYPENAME> out -
add <TYPENAME>_r out <TYPENAME>_mem_data_out
add <TYPENAME>_w in <TYPENAME>_mem_data_in
add <TYPENAME>_wen in <TYPENAME>_mem_valid_in in 'IDLE' stage [NOTE: ORed together with <TYPENAME>_ren]
change <TYPENAME>_len in Used in <TYPENAME>_cnt checks, and to see if collection is empty
The <TYPENAME>_len_latch is removed (Since the Length is now an input).
The 'WRITE_<TYPENAME>' encode_stage is divided with the help of 'cnt' into 2 sub-stages.
The first sub-stage is responsible for requesting the value from the memory (Memory READ request).
The second sub-stage waits until the value is valid (<TYPENAME>_mem_valid_out) and does the usual write
procedure. On sucessfull write the <TYPENAME>_mem_ready_out has to be pulsed high to finalize the memory
operation.
NOTE: If the encode_stage already is divided into sub-stages (due to the primitive type), a single
sub-stage is added that does the Memory fetch operation, and the <TYPENAME>_mem_ready_out is pulled high
in the last sub-stage.
OPTIONALS
=========
The direction of the <TYPENAME>_opt port signal is inverted (in) and the <TYPENAME>_opt_latch is removed.
The memory width is extended by 1 bit, and the <TYPENAME>_opt is prepended
(i.e. <TYPENAME>_mem_data_in <= <TYPENAME>_opt & <TYPENAME>;)
No 'optional' check is done in the respective encode_stage.
An extra sub-stage is added after the memory fetch operation, that writes the optional header depending
on the highest bit of the returned memory value (i.e. the optional bit). If the highest bit is '0' the
optional header gets a length of zero and the encode_stage of the next declared member is selected, else
the actual size of the optional member type is written. The parameter ID of the optional header is
hardcoded to the actual member ID of the optional member.
NOTE: If the optional is part of a collection type, the <TYPENAME>_opt signals are also split into
<TYPENAME>_opt_r and <TYPENAME>_opt_w port signals.
KEY_HOLDER
##########
GENERAL
=======
Generally the key_holder is a combination of both the reader_wrapper and writer_wrapper.
The port signals are predefined and fixed (no port signal generation).
Both encode_stage and decode_stage signals exist.
The 'ALIGN_STREAM' stage is split into 'ALIGN_IN_STREAM' (for decode_stage) and 'ALIGN_OUT_STREAM'
(for encode_stage).
The encoding/decoding follows the definition of the <TOPIC>KeyHolder sub-type definition.[6]
The decode procedure (decode_stage stages) follow the reader_wrapper procedure of the <TOPIC> type until
the last declared member that is also member of the <TOPIC>KeyHolder type, after which the 'SKIP_PAYLOAD'
stage is taken. (Since the serialized key only uses the KeyHolder members, the rest is ignored)
The encode procedure (encode_stage stages) follow the writer_wrapper procedure of the <TOPIC>KeyHolder type.
Since the decode_stages are used to parse both <TOPIC> type data (normal Payloads) and <TOPIC>KeyHolder
type data (Serialized Key), some additional modification have to be done to the decode_stages.
The 'GET_PAYLAOD_HEADER' stage select decode_stage of the first declared member of the <TOPIC> type, while
the 'IDLE' stage (with opcode 'PUSH_SERIALIZED_KEY') selects the decode_stage of the first declared member
of the <TOPIC>KeyHolder type.
All decode_stages use the 'opcode_latch' signal to determine the next decode_stage. When 'opcode_latch'
is 'PUSH_SERIALIZED_KEY', the <TOPIC>KeyHolder type declaration order is followed, else the <TOPIC> type
declaration order.
PITFALLS
########
* Make sure to initialize the 'cnt' signal to zero before calling a decode_stage/encode_stage with sub-stages
[1] DDS_XTYPES v1.3, 7.4.3.1
[2] DDS_XTYPES v1.3, 7.4.1.1.1
[3] DDS_XTYPES v1.3, 7.4.1.1.3
[4] DDS_XTYPES v1.3, 7.4.1.1.4
[5] DDS_XTYPES v1.3, 7.4.1.1.5.2
[6] DDS_XTYPES v1.3, 7.6.8

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.rtps_package.all;
use work.rtps_config_package.all;
use work.Type2_package.all;
architecture TYPE2 of key_holder is
--*****COMPONENT DECLARATION*****
component key_hash_generator is
port (
clk : in std_logic;
reset : in std_logic;
start : in std_logic;
ack : out std_logic;
data_in : in std_logic_vector(7 downto 0);
valid_in : in std_logic;
ready_in : out std_logic;
last_word_in : in std_logic;
key_hash : out std_logic_vector(127 downto 0);
done : out std_logic
);
end component;
--*****TYPE DECLARATION*****
-- FSM states. Explained below in detail
type STAGE_TYPE is (IDLE,START_KEY_HASH_GENERATION,GET_PAYLOAD_HEADER,FETCH,ALIGN_IN_STREAM,SKIP_PAYLOAD,DECODE_PAYLOAD,PUSH,ALIGN_OUT_STREAM,SERIALIZE_KEY,GET_KEY_HASH,PUSH_KEY_HASH);
-- ###GENERATED START###
type DECODE_STAGE_TYPE is (GET_OPTIONAL_HEADER, TODO);
type ENCODE_STAGE_TYPE is (TODO);
-- TYPES DECLARATIONS
-- ###GENERATED END###
-- *MAIN PROCESS*
signal stage, stage_next : STAGE_TYPE := IDLE;
signal cnt, cnt_next : natural range 0 to 5 := 0;
signal endian_flag, endian_flag_next : std_logic := '0';
signal last_word_in_latch, last_word_in_latch_next : std_logic := '0';
signal decode_error_latch, decode_error_latch_next : std_logic := '0';
signal align_offset, align_offset_next : unsigned(MAX_ALIGN_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal target_align, target_align_next : ALIGN_TYPE := ALIGN_1;
signal data_in_latch, data_in_latch_next : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal data_out_latch, data_out_latch_next : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal optional, optional_next : std_logic := '0';
signal abort_mem : std_logic := '0';
signal opcode_latch, opcode_latch_next : KEY_HOLDER_OPCODE_TYPE := NOP;
signal cnt_2, cnt_2_next : natural range 0 to (WORD_WIDTH/BYTE_WIDTH)-1 := 0;
signal align_op, align_op_next : std_logic := '0';
signal finalize_payload, finalize_payload_next : std_logic := '0';
signal ready_in_sig : std_logic := '0';
signal start_kh, ack_kh, done_kh : std_logic := '0';
signal data_in_kh : std_logic_vector(BYTE_WIDTH-1 downto 0) := (others => '0');
signal valid_in_kh, ready_in_kh, last_word_in_kh : std_logic := '0';
signal key_hash_kh : std_logic_vector(KEY_HASH_WIDTH-1 downto 0) := (others => '0');
signal key_hash, key_hash_next : KEY_HASH_TYPE := HANDLE_NIL;
signal decode_stage, decode_stage_next : DECODE_STAGE_TYPE := TODO;
signal encode_stage, encode_stage_next : ENCODE_STAGE_TYPE := TODO;
signal return_stage, return_stage_next : DECODE_STAGE_TYPE := TODO;
-- ###GENERATED START###
-- SIGNAL DECLARATION
-- ###GENERATED END###
--*****ALIAS DECLARATION*****
alias representation_id : std_logic_vector(PAYLOAD_REPRESENTATION_ID_WIDTH-1 downto 0) is data_in(WORD_WIDTH-1 downto WORD_WIDTH-PAYLOAD_REPRESENTATION_ID_WIDTH);
alias representation_options : std_logic_vector(PAYLOAD_REPRESENTATION_ID_WIDTH-1 downto 0) is data_in(PAYLOAD_REPRESENTATION_OPTIONS_WIDTH-1 downto 0);
alias parameter_id : std_logic_vector(PARAMETER_ID_WIDTH-1 downto 0) is data_in_latch(WORD_WIDTH-1 downto WORD_WIDTH-PARAMETER_ID_WIDTH);
alias parameter_length : std_logic_vector(PARAMETER_LENGTH_WIDTH-1 downto 0) is data_in_latch(PARAMETER_LENGTH_WIDTH-1 downto 0);
begin
key_hash_generator_inst : key_hash_generator
port map (
clk => clk,
reset => reset,
start => start_kh,
ack => ack_kh,
data_in => data_in_kh,
valid_in => valid_in_kh,
ready_in => ready_in_kh,
last_word_in => last_word_in_kh,
key_hash => key_hash_kh,
done => done_kh
);
-- ###GENERATED START###
-- MEMORY INSTANTIATIONS
-- ###GENERATED END###
decode_error <= decode_error_latch;
ready_in <= ready_in_sig;
main_prc : process (all)
variable tmp_length : unsigned(WORD_WIDTH-1 downto 0) := (others => '0');
begin
-- DEFAULT
stage_next <= stage;
decode_stage_next <= decode_stage;
encode_stage_next <= encode_stage;
return_stage_next <= return_stage;
cnt_next <= cnt;
cnt_2_next <= cnt_2;
endian_flag_next <= endian_flag;
last_word_in_latch_next <= last_word_in_latch;
decode_error_latch_next <= decode_error_latch;
align_offset_next <= align_offset;
target_align_next <= target_align;
optional_next <= optional;
data_in_latch_next <= data_in_latch;
data_out_latch_next <= data_out_latch;
opcode_latch_next <= opcode_latch;
key_hash_next <= key_hash;
align_op_next <= align_op;
finalize_payload_next <= finalize_payload;
abort_mem <= '0';
ack <= '0';
ready_in_sig <= '0';
last_word_out <= '0';
valid_out <= '0';
start_kh <= '0';
valid_in_kh <= '0';
data_in_kh <= (others => '0');
data_out <= (others => '0');
-- ###GENERATED START###
-- DEFAULT SIGNAL ASSIGNMENTS
-- ###GENERATED END###
-- Last Word Latch Setter
if (last_word_in = '1') then
last_word_in_latch_next <= '1';
end if;
case (stage) is
when IDLE =>
-- Latch Opcode
opcode_latch_next <= opcode;
if (start = '1') then
case (opcode) is
when PUSH_DATA =>
ack <= '1';
stage_next <= GET_PAYLOAD_HEADER;
-- Reset
key_hash_next <= HANDLE_NIL;
when PUSH_SERIALIZED_KEY =>
ack <= '1';
-- Serialized Key is in PLAIN_CDR2 Big Endian encoding
endian_flag_next <= '0';
stage_next <= FETCH;
-- Alignment Reset
align_offset_next <= (others => '0');
-- ###GENERATED START###
decode_stage_next <= TODO;
-- ###GENERATED END###
when READ_KEY_HASH =>
ack <= '1';
-- Key Hash not calculated
if (key_hash = HANDLE_NIL) then
stage_next <= START_KEY_HASH_GENERATION;
else
stage_next <= PUSH_KEY_HASH;
cnt_next <= 0;
end if;
when READ_SERIALIZED_KEY =>
ack <= '1';
stage_next <= SERIALIZE_KEY;
-- Alignment Reset
align_offset_next <= (others => '0');
data_out_latch_next <= (others => '0');
-- ###GENERATED START###
encode_stage_next <= TODO;
-- ###GENERATED END###
when others =>
null;
end case;
end if;
when START_KEY_HASH_GENERATION =>
start_kh <= '1';
if (ack_kh = '1') then
stage_next <= SERIALIZE_KEY;
-- ###GENERATED START###
encode_stage_next <= TODO;
-- ###GENERATED END###
end if;
when GET_PAYLOAD_HEADER =>
-- TODO: Latch Offset from Options Field?
ready_in_sig <= '1';
-- Input Guard
if (valid_in = '1') then
case (representation_id) is
when CDR_BE =>
endian_flag_next <= '0';
stage_next <= FETCH;
-- Alignment Reset
align_offset_next <= (others => '0');
-- ###GENERATED START###
decode_stage_next <= TODO;
-- ###GENERATED END###
when CDR_LE =>
endian_flag_next <= '1';
stage_next <= FETCH;
-- Alignment Reset
align_offset_next <= (others => '0');
-- ###GENERATED START###
decode_stage_next <= TODO;
-- ###GENERATED END###
when others =>
-- Unknown Payload Encoding
stage_next <= SKIP_PAYLOAD;
decode_error_latch_next <= '1';
end case;
end if;
when FETCH =>
ready_in_sig <= '1';
-- Input Guard
if (valid_in = '1') then
data_in_latch_next <= data_in;
-- Alignment Operation in progress
if (align_op = '1') then
stage_next <= ALIGN_IN_STREAM;
-- Reset
align_op_next <= '0';
else
stage_next <= DECODE_PAYLOAD;
end if;
end if;
when ALIGN_IN_STREAM =>
-- Target Stream Alignment reached
if (check_align(align_offset, target_align)) then
-- DONE
stage_next <= DECODE_PAYLOAD;
else
align_offset_next <= align_offset + 1;
-- Need to fetch new Input Word
if (align_offset(1 downto 0) = "11") then
align_op_next <= '1';
stage_next <= FETCH;
end if;
end if;
when SKIP_PAYLOAD =>
if (last_word_in_latch = '0') then
-- Skip Read
ready_in_sig <= '1';
else
stage_next <= IDLE;
-- Reset
last_word_in_latch_next <= '0';
end if;
when DECODE_PAYLOAD =>
case (decode_stage) is
-- ###GENERATED START###
when TODO =>
-- ###GENERATED END###
when GET_OPTIONAL_HEADER =>
-- ALIGN GUARD
if (not check_align(align_offset, ALIGN_4)) then
target_align_next <= ALIGN_4;
stage_next <= ALIGN_IN_STREAM;
else
case (cnt) is
-- Optional Member Header
when 0 =>
-- Extended Parameter Header
if (endian_swap(endian_flag,parameter_id) = PID_EXTENDED) then
cnt_next <= cnt + 1;
stage_next <= FETCH;
else
stage_next <= FETCH;
decode_stage_next <= return_stage;
cnt_next <= 0;
-- Alignment Reset
align_offset_next <= (others => '0');
-- Optional omitted
if(endian_swap(endian_flag,parameter_length) = (parameter_length'reverse_range => '0')) then
optional_next <= '0';
else
optional_next <= '1';
end if;
end if;
-- eMemberHeader
when 1 =>
-- Ignore Parameter ID
cnt_next <= cnt + 1;
stage_next <= FETCH;
-- Llength
when 2 =>
stage_next <= FETCH;
decode_stage_next <= return_stage;
cnt_next <= 0;
-- Alignment Reset
align_offset_next <= (others => '0');
-- Optional omitted
if(endian_swap(endian_flag, data_in) = (data_in'reverse_range => '0')) then
optional_next <= '0';
else
optional_next <= '1';
end if;
when others =>
null;
end case;
end if;
when others =>
null;
end case;
when PUSH =>
-- Push to Key Hash Generator
if (opcode_latch = READ_KEY_HASH) then
-- Mark Last Word
if (finalize_payload = '1' and cnt_2 = to_integer(unsigned(align_offset(1 downto 0)))) then
last_word_in_kh <= '1';
end if;
valid_in_kh <= '1';
data_in_kh <= get_sub_vector(data_out_latch, cnt_2, BYTE_WIDTH, TRUE);
-- Output Guard
if (ready_in_kh = '1') then
-- Last Byte
if ((finalize_payload = '1' and cnt_2 = to_integer(unsigned(align_offset(1 downto 0)))) or cnt_2 = (WORD_WIDTH/BYTE_WIDTH)-1) then
-- Reset
cnt_2_next <= 0;
-- Alignment Operation in process
if (align_op = '1') then
stage_next <= ALIGN_OUT_STREAM;
-- Reset
align_op_next <= '0';
-- DONE
elsif (finalize_payload = '1') then
stage_next <= GET_KEY_HASH;
-- Reset
finalize_payload_next <= '0';
else
stage_next <= SERIALIZE_KEY;
end if;
else
cnt_2_next <= cnt_2 + 1;
end if;
end if;
else
-- Mark Last Word
if (finalize_payload = '1') then
last_word_out <= '1';
end if;
valid_out <= '1';
data_out <= data_out_latch;
-- Output Guard
if (ready_out = '1') then
-- NOTE: Ensures all padding is zero.
data_out_latch_next <= (others => '0');
-- Alignment Operation in process
if (align_op = '1') then
stage_next <= ALIGN_OUT_STREAM;
-- Reset
align_op_next <= '0';
-- DONE
elsif (finalize_payload = '1') then
finalize_payload_next <= '0';
stage_next <= IDLE;
else
stage_next <= SERIALIZE_KEY;
end if;
end if;
end if;
when ALIGN_OUT_STREAM =>
-- Target Stream Alignment reached
if (check_align(align_offset, target_align)) then
-- DONE
stage_next <= SERIALIZE_KEY;
else
align_offset_next <= align_offset + 1;
-- Need to push Word
if (align_offset(1 downto 0) = "11") then
align_op_next <= '1';
stage_next <= PUSH;
end if;
end if;
when SERIALIZE_KEY =>
case (encode_stage) is
-- ###GENERATED START###
when TODO =>
-- ###GENERATED END###
when others =>
end case;
when GET_KEY_HASH =>
if (done_kh = '1') then
key_hash_next <= to_key_hash(key_hash_kh);
stage_next <= PUSH_KEY_HASH;
cnt_next <= 0;
end if;
when PUSH_KEY_HASH =>
case (cnt) is
-- Key Hash 1/4
when 0 =>
data_out <= key_hash(0);
valid_out <= '1';
-- Output Guard
if (ready_out = '1') then
cnt_next <= cnt + 1;
end if;
-- Key Hash 2/4
when 1 =>
data_out <= key_hash(1);
valid_out <= '1';
-- Output Guard
if (ready_out = '1') then
cnt_next <= cnt + 1;
end if;
-- Key Hash 3/4
when 2 =>
data_out <= key_hash(2);
valid_out <= '1';
-- Output Guard
if (ready_out = '1') then
cnt_next <= cnt + 1;
end if;
-- Key Hash 4/4
when 3 =>
data_out <= key_hash(3);
valid_out <= '1';
last_word_out <= '1';
-- Output Guard
if (ready_out = '1') then
-- DONE
stage_next <= IDLE;
end if;
when others =>
null;
end case;
when others =>
null;
end case;
-- OVERREAD GUARD
-- Attempted read on empty input
if (last_word_in_latch = '1' and last_word_in = '0' and ready_in_sig = '1') then
stage_next <= SKIP_PAYLOAD;
decode_error_latch_next <= '1';
end if;
end process;
sync_prc : process(clk)
begin
if rising_edge(clk) then
if (reset = '1') then
stage <= IDLE;
decode_stage <= TODO;
encode_stage <= TODO;
return_stage <= TODO;
target_align <= ALIGN_1;
opcode_latch <= NOP;
cnt <= 0;
cnt_2 <= 0;
endian_flag <= '0';
last_word_in_latch <= '0';
decode_error_latch <= '0';
optional <= '0';
align_op <= '0';
finalize_payload <= '0';
align_offset <= (others => '0');
data_in_latch <= (others => '0');
data_out_latch <= (others => '0');
key_hash <= HANDLE_NIL;
-- ###GENERATED START###
-- RESET SYNC SIGNAL VALUE
-- ###GENERATED END###
else
stage <= stage_next;
decode_stage <= decode_stage_next;
encode_stage <= encode_stage_next;
return_stage <= return_stage_next;
target_align <= target_align_next;
opcode_latch <= opcode_latch_next;
cnt <= cnt_next;
cnt_2 <= cnt_2_next;
endian_flag <= endian_flag_next;
last_word_in_latch <= last_word_in_latch_next;
decode_error_latch <= decode_error_latch_next;
optional <= optional_next;
align_op <= align_op_next;
finalize_payload <= finalize_payload_next;
align_offset <= align_offset_next;
data_in_latch <= data_in_latch_next;
data_out_latch <= data_out_latch_next;
key_hash <= key_hash_next;
-- ###GENERATED START###
-- SYNC SIGNALS
-- ###GENERATED END###
end if;
end if;
end process;
end architecture;

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.rtps_package.all;
use work.rtps_config_package.all;
use work.Type2_package.all;
entity Type2_reader_wrapper is
port (
-- SYSTEM
clk : in std_logic;
reset : in std_logic;
-- FROM DDS READER
start_dds : out std_logic;
ack_dds : in std_logic;
opcode_dds : out DDS_READER_OPCODE_TYPE;
instance_state_dds : out std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0);
view_state_dds : out std_logic_vector(VIEW_STATE_KIND_WIDTH-1 downto 0);
sample_state_dds : out std_logic_vector(SAMPLE_STATE_KIND_WIDTH-1 downto 0);
instance_handle_dds : out INSTANCE_HANDLE_TYPE;
max_samples_dds : out std_logic_vector(MAX_SAMPLES_WIDTH-1 downto 0);
get_data_dds : out std_logic;
done_dds : in std_logic;
return_code_dds : in std_logic_vector(RETURN_CODE_WIDTH-1 downto 0);
ready_in_dds : out std_logic;
valid_in_dds : in std_logic;
data_in_dds : in std_logic_vector(WORD_WIDTH-1 downto 0);
last_word_in_dds : in std_logic;
-- Sample Info
si_sample_state_dds : in std_logic_vector(SAMPLE_STATE_KIND_WIDTH-1 downto 0);
si_view_state_dds : in std_logic_vector(VIEW_STATE_KIND_WIDTH-1 downto 0);
si_instance_state_dds : in std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0);
si_source_timestamp_dds : in TIME_TYPE;
si_instance_handle_dds : in INSTANCE_HANDLE_TYPE;
si_publication_handle_dds : in PUBLICATION_HANDLE_TYPE;
si_disposed_generation_count_dds : in std_logic_vector(DISPOSED_GENERATION_COUNT_WIDTH-1 downto 0);
si_no_writers_generation_count_dds : in std_logic_vector(NO_WRITERS_GENERATION_COUNT_WIDTH-1 downto 0);
si_sample_rank_dds : in std_logic_vector(SAMPLE_RANK_WIDTH-1 downto 0);
si_generation_rank_dds : in std_logic_vector(GENERATION_RANK_WIDTH-1 downto 0);
si_absolute_generation_rank_dds : in std_logic_vector(ABSOLUTE_GENERATION_COUNT_WIDTH-1 downto 0);
si_valid_data_dds : in std_logic;
si_valid_dds : in std_logic;
si_ack_dds : out std_logic;
eoc_dds : in std_logic;
-- Communication Status
status_dds : in std_logic_vector(STATUS_KIND_WIDTH-1 downto 0);
-- TO USER ENTITY
start_user : in std_logic;
ack_user : out std_logic;
opcode_user : in DDS_READER_OPCODE_TYPE;
instance_state_user : in std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0);
view_state_user : in std_logic_vector(VIEW_STATE_KIND_WIDTH-1 downto 0);
sample_state_user : in std_logic_vector(SAMPLE_STATE_KIND_WIDTH-1 downto 0);
instance_handle_user : in INSTANCE_HANDLE_TYPE;
max_samples_user : in std_logic_vector(MAX_SAMPLES_WIDTH-1 downto 0);
get_data_user : in std_logic;
done_user : out std_logic;
return_code_user : out std_logic_vector(RETURN_CODE_WIDTH-1 downto 0);
-- Sample Info
si_sample_state_user : out std_logic_vector(SAMPLE_STATE_KIND_WIDTH-1 downto 0);
si_view_state_user : out std_logic_vector(VIEW_STATE_KIND_WIDTH-1 downto 0);
si_instance_state_user : out std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0);
si_source_timestamp_user : out TIME_TYPE;
si_instance_handle_user : out INSTANCE_HANDLE_TYPE;
si_publication_handle_user : out PUBLICATION_HANDLE_TYPE;
si_disposed_generation_count_user : out std_logic_vector(DISPOSED_GENERATION_COUNT_WIDTH-1 downto 0);
si_no_writers_generation_count_user : out std_logic_vector(NO_WRITERS_GENERATION_COUNT_WIDTH-1 downto 0);
si_sample_rank_user : out std_logic_vector(SAMPLE_RANK_WIDTH-1 downto 0);
si_generation_rank_user : out std_logic_vector(GENERATION_RANK_WIDTH-1 downto 0);
si_absolute_generation_rank_user : out std_logic_vector(ABSOLUTE_GENERATION_COUNT_WIDTH-1 downto 0);
si_valid_data_user : out std_logic;
si_valid_user : out std_logic;
si_ack_user : in std_logic;
eoc_user : out std_logic;
-- Communication Status
status_user : out std_logic_vector(STATUS_KIND_WIDTH-1 downto 0);
decode_error : out std_logic;
-- ###GENERATED START###
-- TYPE SPECIFIC PORTS
-- ###GENERATED END###
valid : out std_logic
);
end entity;
architecture arch of Type2_reader_wrapper is
--*****TYPE DECLARATION*****
-- FSM states. Explained below in detail
type STAGE_TYPE is (IDLE,GET_PAYLOAD_HEADER,FETCH,ALIGN_STREAM,SKIP_PAYLOAD,DECODE_PAYLOAD);
-- ###GENERATED START###
type DECODE_STAGE_TYPE is (GET_OPTIONAL_HEADER);
-- TYPES DECLARATIONS
-- ###GENERATED END###
-- *MAIN PROCESS*
signal stage, stage_next : STAGE_TYPE := IDLE;
signal cnt, cnt_next : natural range 0 to 5 := 0;
signal endian_flag, endian_flag_next : std_logic := '0';
signal last_word_in_latch, last_word_in_latch_next : std_logic := '0';
signal decode_error_latch, decode_error_latch_next : std_logic := '0';
signal align_offset, align_offset_next : unsigned(MAX_ALIGN_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal align_op, align_op_next : std_logic := '0';
signal target_align, target_align_next : ALIGN_TYPE := ALIGN_1;
signal data_in_latch, data_in_latch_next : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal optional, optional_next : std_logic := '0';
signal abort_mem : std_logic := '0';
signal ready_in_dds_sig : std_logic := '0';
signal valid_latch, valid_latch_next : std_logic := '0';
signal decode_stage, decode_stage_next : DECODE_STAGE_TYPE := TODO;
signal return_stage, return_stage_next : DECODE_STAGE_TYPE := TODO;
-- ###GENERATED START###
-- SIGNAL DECLARATIONS
-- ###GENERATED END###
--*****ALIAS DECLARATION*****
alias representation_id : std_logic_vector(PAYLOAD_REPRESENTATION_ID_WIDTH-1 downto 0) is data_in_dds(WORD_WIDTH-1 downto WORD_WIDTH-PAYLOAD_REPRESENTATION_ID_WIDTH);
alias representation_options : std_logic_vector(PAYLOAD_REPRESENTATION_ID_WIDTH-1 downto 0) is data_in_dds(PAYLOAD_REPRESENTATION_OPTIONS_WIDTH-1 downto 0);
alias parameter_id : std_logic_vector(PARAMETER_ID_WIDTH-1 downto 0) is data_in_latch(WORD_WIDTH-1 downto WORD_WIDTH-PARAMETER_ID_WIDTH);
alias parameter_length : std_logic_vector(PARAMETER_LENGTH_WIDTH-1 downto 0) is data_in_latch(PARAMETER_LENGTH_WIDTH-1 downto 0);
begin
-- ###GENERATED START###
-- MEMORY INSTANTIATIONS
-- ###GENERATED END###
-- PASSTHROUGH
start_dds <= start_user;
ack_user <= ack_dds;
opcode_dds <= opcode_user;
instance_state_dds <= instance_state_user;
view_state_dds <= view_state_user;
sample_state_dds <= sample_state_user;
instance_handle_dds <= instance_handle_user;
max_samples_dds <= max_samples_user;
get_data_dds <= get_data_user;
done_user <= done_dds;
return_code_user <= return_code_dds;
si_sample_state_user <= si_sample_state_dds;
si_view_state_user <= si_view_state_dds;
si_instance_state_user <= si_instance_state_dds;
si_source_timestamp_user <= si_source_timestamp_dds;
si_instance_handle_user <= si_instance_handle_dds;
si_publication_handle_user <= si_publication_handle_dds;
si_disposed_generation_count_user <= si_disposed_generation_count_dds;
si_no_writers_generation_count_user <= si_no_writers_generation_count_dds;
si_sample_rank_user <= si_sample_rank_dds;
si_generation_rank_user <= si_generation_rank_dds;
si_absolute_generation_rank_user <= si_absolute_generation_rank_dds;
si_valid_data_user <= si_valid_data_dds;
si_valid_user <= si_valid_dds;
si_ack_dds <= si_ack_user;
eoc_user <= eoc_dds;
status_user <= status_dds;
valid <= valid_latch;
decode_error <= decode_error_latch;
ready_in_dds <= ready_in_dds_sig;
-- ###GENERATED START###
-- PORT SIGNAL CONNECTIONS
-- ###GENERATED END###
main_prc : process (all)
variable tmp_length : unsigned(WORD_WIDTH-1 downto 0) := (others => '0');
begin
-- DEFAULT
stage_next <= stage;
decode_stage_next <= decode_stage;
return_stage_next <= return_stage;
cnt_next <= cnt;
endian_flag_next <= endian_flag;
last_word_in_latch_next <= last_word_in_latch;
decode_error_latch_next <= decode_error_latch;
align_offset_next <= align_offset;
target_align_next <= target_align;
optional_next <= optional;
valid_latch_next <= valid_latch;
data_in_latch_next <= data_in_latch;
align_op_next <= align_op;
abort_mem <= '0';
ready_in_dds_sig <= '0';
-- ###GENERATED START###
-- DEFAULT SIGNAL ASSIGNMENTS
-- ###GENERATED END###
-- Last Word Latch Setter
if (last_word_in_dds = '1') then
last_word_in_latch_next <= '1';
end if;
case (stage) is
when IDLE =>
-- User Requests Payload
if (si_valid_dds = '1' and si_valid_data_dds = '1' and si_ack_user = '1' and get_data_user = '1') then
stage_next <= GET_PAYLOAD_HEADER;
-- RESET
decode_error_latch_next <= '0';
valid_latch_next <= '0';
abort_mem <= '1';
else
-- ###GENERATED START###
-- MEMORY SIGNAL CONNECTIONS
-- ###GENERATED END###
end if;
when GET_PAYLOAD_HEADER =>
-- TODO: Latch Offset from Options Field?
ready_in_dds_sig <= '1';
-- Input Guard
if (valid_in_dds = '1') then
case (representation_id) is
when CDR_BE =>
endian_flag_next <= '0';
stage_next <= FETCH;
-- Alignment Reset
align_offset_next <= (others => '0');
-- ###GENERATED START###
decode_stage_next <= TODO;
-- ###GENERATED END###
-- Initial Fetch
when CDR_LE =>
endian_flag_next <= '1';
stage_next <= FETCH;
-- Alignment Reset
align_offset_next <= (others => '0');
-- ###GENERATED START###
decode_stage_next <= TODO;
-- ###GENERATED END###
when others =>
-- Unknown Payload Encoding
stage_next <= SKIP_PAYLOAD;
decode_error_latch_next <= '1';
end case;
end if;
when FETCH =>
ready_in_dds_sig <= '1';
-- Input Guard
if (valid_in_dds = '1') then
data_in_latch_next <= data_in_dds;
-- Alignment Operation in progress
if (align_op = '1') then
stage_next <= ALIGN_STREAM;
-- Reset
align_op_next <= '0';
else
stage_next <= DECODE_PAYLOAD;
end if;
end if;
when ALIGN_STREAM =>
-- Target Stream Alignment reached
if (check_align(align_offset, target_align)) then
-- DONE
stage_next <= DECODE_PAYLOAD;
else
align_offset_next <= align_offset + 1;
-- Need to fetch new Input Word
if (align_offset(1 downto 0) = "11") then
align_op_next <= '1';
stage_next <= FETCH;
end if;
end if;
when SKIP_PAYLOAD =>
if (last_word_in_latch = '0' and last_word_in_dds = '0') then
-- Skip Read
ready_in_dds_sig <= '1';
else
stage_next <= IDLE;
-- If no Decode Error, mark output as valid
if (decode_error_latch = '0') then
valid_latch_next <= '1';
end if;
-- Reset
last_word_in_latch_next <= '0';
end if;
when DECODE_PAYLOAD =>
case (decode_stage) is
-- ###GENERATED START###
when TODO =>
-- ###GENERATED END###
when GET_OPTIONAL_HEADER =>
-- ALIGN GUARD
if (not check_align(align_offset, ALIGN_4)) then
target_align_next <= ALIGN_4;
stage_next <= ALIGN_STREAM;
else
case (cnt) is
-- Optional Member Header
when 0 =>
-- Extended Parameter Header
if (endian_swap(endian_flag,parameter_id) = PID_EXTENDED) then
cnt_next <= cnt + 1;
stage_next <= FETCH;
else
stage_next <= FETCH;
decode_stage_next <= return_stage;
cnt_next <= 0;
-- Alignment Reset
align_offset_next <= (others => '0');
-- Optional omitted
if(endian_swap(endian_flag,parameter_length) = (parameter_length'reverse_range => '0')) then
optional_next <= '0';
else
optional_next <= '1';
end if;
end if;
-- eMemberHeader
when 1 =>
-- Ignore Parameter ID
cnt_next <= cnt + 1;
stage_next <= FETCH;
-- Llength
when 2 =>
stage_next <= FETCH;
decode_stage_next <= return_stage;
cnt_next <= 0;
-- Alignment Reset
align_offset_next <= (others => '0');
-- Optional omitted
if(endian_swap(endian_flag, data_in_dds) = (data_in_dds'reverse_range => '0')) then
optional_next <= '0';
else
optional_next <= '1';
end if;
when others =>
null;
end case;
end if;
when others =>
null;
end case;
when others =>
null;
end case;
-- OVERREAD GUARD
-- Attempted read on empty input
if (last_word_in_latch = '1' and last_word_in_dds = '0' and ready_in_dds_sig = '1') then
stage_next <= SKIP_PAYLOAD;
decode_error_latch_next <= '1';
end if;
end process;
sync_prc : process(clk)
begin
if rising_edge(clk) then
if (reset = '1') then
stage <= IDLE;
decode_stage <= TODO;
return_stage <= TODO;
target_align <= ALIGN_1;
cnt <= 0;
endian_flag <= '0';
last_word_in_latch <= '0';
decode_error_latch <= '0';
optional <= '0';
valid_latch <= '0';
align_op <= '0';
align_offset <= (others => '0');
data_in_latch <= (others => '0');
-- ###GENERATED START###
-- RESET SYNC SIGNAL VALUE
-- ###GENERATED END###
else
stage <= stage_next;
decode_stage <= decode_stage_next;
return_stage <= return_stage_next;
target_align <= target_align_next;
cnt <= cnt_next;
endian_flag <= endian_flag_next;
last_word_in_latch <= last_word_in_latch_next;
decode_error_latch <= decode_error_latch_next;
optional <= optional_next;
valid_latch <= valid_latch_next;
align_op <= align_op_next;
align_offset <= align_offset_next;
data_in_latch <= data_in_latch_next;
-- ###GENERATED START###
-- SYNC SIGNALS
-- ###GENERATED END###
end if;
end if;
end process;
end architecture;

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.rtps_package.all;
use work.rtps_config_package.all;
use work.Type2_package.all;
entity Type2_writer_wrapper is
generic (
LITTLE_ENDIAN : std_logic := '0'
);
port (
-- SYSTEM
clk : in std_logic;
reset : in std_logic;
-- FROM DDS WRITER
start_dds : out std_logic;
ack_dds : in std_logic;
opcode_dds : out DDS_WRITER_OPCODE_TYPE;
instance_handle_dds : out INSTANCE_HANDLE_TYPE;
source_ts_dds : out TIME_TYPE;
max_wait_dds : out DURATION_TYPE;
done_dds : in std_logic;
return_code_dds : in std_logic_vector(RETURN_CODE_WIDTH-1 downto 0);
ready_out_dds : in std_logic;
valid_out_dds : out std_logic;
data_out_dds : out std_logic_vector(WORD_WIDTH-1 downto 0);
last_word_out_dds : out std_logic;
ready_in_dds : out std_logic;
valid_in_dds : in std_logic;
data_in_dds : in std_logic_vector(WORD_WIDTH-1 downto 0);
last_word_in_dds : in std_logic;
-- Communication Status
status_dds : in std_logic_vector(STATUS_KIND_WIDTH-1 downto 0);
-- TO USER ENTITY
start_user : in std_logic;
ack_user : out std_logic;
opcode_user : in DDS_WRITER_OPCODE_TYPE;
instance_handle_user : in INSTANCE_HANDLE_TYPE;
source_ts_user : in TIME_TYPE;
max_wait_user : in DURATION_TYPE;
done_user : out std_logic;
return_code_user : out std_logic_vector(RETURN_CODE_WIDTH-1 downto 0);
ready_out_user : in std_logic;
valid_out_user : out std_logic;
data_out_user : out std_logic_vector(WORD_WIDTH-1 downto 0);
last_word_out_user : out std_logic;
-- Communication Status
status_user : out std_logic_vector(STATUS_KIND_WIDTH-1 downto 0);
-- ###GENERATED START###
-- TYPE SPECIFIC PORTS
-- ###GENERATED END###
encode_done : out std_logic
);
end entity;
architecture arch of Type2_writer_wrapper is
--*****TYPE DECLARATION*****
-- FSM states. Explained below in detail
type STAGE_TYPE is (IDLE,WRITE_PAYLOAD_HEADER,PUSH,ALIGN_STREAM,ENCODE_PAYLOAD);
-- ###GENERATED START###
type ENCODE_STAGE_TYPE is (TODO);
-- TYPES DECLARATIONS
-- ###GENERATED END###
-- *MAIN PROCESS*
signal stage, stage_next : STAGE_TYPE := IDLE;
signal cnt, cnt_next : natural range 0 to 5 := 0;
signal align_offset, align_offset_next : unsigned(MAX_ALIGN_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal align_op, align_op_next : std_logic := '0';
signal target_align, target_align_next : ALIGN_TYPE := ALIGN_1;
signal data_out_latch, data_out_latch_next : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal abort_mem : std_logic := '0';
signal finalize_payload, finalize_payload_next : std_logic := '0';
signal encode_stage, encode_stage_next : ENCODE_STAGE_TYPE := TODO;
-- ###GENERATED START###
-- SIGNAL DECLARATION
-- ###GENERATED END###
begin
-- ###GENERATED START###
-- MEMORY INSTANTIATIONS
-- ###GENERATED END###
-- PASSTHROUGH
start_dds <= start_user;
ack_user <= ack_dds;
opcode_dds <= opcode_user;
instance_handle_dds <= instance_handle_user;
source_ts_dds <= source_ts_user;
max_wait_dds <= max_wait_user;
done_user <= done_dds;
return_code_user <= return_code_dds;
ready_in_dds <= ready_out_user;
valid_out_user <= valid_in_dds;
data_out_user <= data_in_dds;
last_word_out_user <= last_word_in_dds;
status_user <= status_dds;
-- ###GENERATED START###
-- PORT SIGNAL CONNECTIONS
-- ###GENERATED END###
main_prc : process (all)
variable tmp_length : unsigned(WORD_WIDTH-1 downto 0) := (others => '0');
begin
-- DEFAULT
stage_next <= stage;
encode_stage_next <= encode_stage;
cnt_next <= cnt;
align_offset_next <= align_offset;
align_op_next <= align_op;
target_align_next <= target_align;
data_out_latch_next <= data_out_latch;
finalize_payload_next <= finalize_payload;
abort_mem <= '0';
encode_done <= '0';
valid_out_dds <= '0';
last_word_out_dds <= '0';
data_out_dds <= (others => '0');
-- ###GENERATED START###
-- DEFAULT SIGNAL ASSIGNMENTS
-- ###GENERATED END###
case (stage) is
when IDLE =>
-- User Requests Payload
if (start_user = '1' and ack_dds = '1') then
case (opcode_user) is
when REGISTER_INSTANCE =>
stage_next <= WRITE_PAYLOAD_HEADER;
-- RESET
abort_mem <= '1';
when UNREGISTER_INSTANCE =>
stage_next <= WRITE_PAYLOAD_HEADER;
-- RESET
abort_mem <= '1';
when LOOKUP_INSTANCE =>
stage_next <= WRITE_PAYLOAD_HEADER;
-- RESET
abort_mem <= '1';
when WRITE =>
stage_next <= WRITE_PAYLOAD_HEADER;
-- RESET
abort_mem <= '1';
when DISPOSE =>
stage_next <= WRITE_PAYLOAD_HEADER;
-- RESET
abort_mem <= '1';
when others =>
null;
end case;
else
-- ###GENERATED START###
-- MEMORY SIGNAL CONNECTIONS
-- ###GENERATED END###
end if;
when WRITE_PAYLOAD_HEADER =>
if (LITTLE_ENDIAN = '0') then
data_out_latch_next <= CDR_BE & x"0000";
else
data_out_latch_next <= CDR_LE & x"0000";
end if;
stage_next <= PUSH;
-- ###GENERATED START###
encode_stage_next <= TODO;
-- ###GENERATED END###
when PUSH =>
-- Mark Last Word
if (finalize_payload = '1') then
last_word_out_dds <= '1';
end if;
valid_out_dds <= '1';
data_out_dds <= data_out_latch;
-- Output Guard
if (ready_out_dds = '1') then
-- NOTE: Ensures all padding is zero.
data_out_latch_next <= (others => '0');
-- Alignment Operation in process
if (align_op = '1') then
stage_next <= ALIGN_STREAM;
-- Reset
align_op_next <= '0';
-- DONE
elsif (finalize_payload = '1') then
finalize_payload_next <= '0';
stage_next <= IDLE;
else
stage_next <= ENCODE_PAYLOAD;
end if;
end if;
when ALIGN_STREAM =>
-- Target Stream Alignment reached
if (check_align(align_offset, target_align)) then
-- DONE
stage_next <= ENCODE_PAYLOAD;
else
align_offset_next <= align_offset + 1;
-- Need to push Word
if (align_offset(1 downto 0) = "11") then
align_op_next <= '1';
stage_next <= PUSH;
end if;
end if;
when ENCODE_PAYLOAD =>
case (encode_stage) is
-- ###GENERATED START###
when TODO =>
-- ###GENERATED END###
when others =>
null;
end case;
when others =>
null;
end case;
end process;
sync_prc : process(clk)
begin
if rising_edge(clk) then
if (reset = '1') then
stage <= IDLE;
encode_stage <= TODO;
target_align <= ALIGN_1;
cnt <= 0;
finalize_payload <= '0';
align_op <= '0';
align_offset <= (others => '0');
data_out_latch <= (others => '0');
-- ###GENERATED START###
-- RESET SYNC SIGNAL VALUE
-- ###GENERATED END###
else
stage <= stage_next;
encode_stage <= encode_stage_next;
target_align <= target_align_next;
cnt <= cnt_next;
finalize_payload <= finalize_payload_next;
align_op <= align_op_next;
align_offset <= align_offset_next;
data_out_latch <= data_out_latch_next;
-- ###GENERATED START###
-- SYNC SIGNALS
-- ###GENERATED END###
end if;
end if;
end process;
end architecture;

33
src/TODO.txt
View File

@ -42,6 +42,8 @@
* Use generic package with unconstrained arrays (VHDL-2008), and assert bounds/length inside the package.
* Count repository lines
git ls-files | grep .vhd | xargs wc -l
# Without Tests
git ls-files | grep .vhd | grep -v Tests | xargs wc -l
* Count Field in Heartbeat/Acknack
The following sentence is quite self-explanatory:
"A counter that is incremented each time a new message is sent. Provides the means to detect
@ -82,6 +84,12 @@
* The Participant GUID of the ParticipantMessageData is theoretically not needed, since it is the same as the source GUID of the Packet. This is done, so that the ParticipantMessageData has a key and can be decrypted as every other DATA Message. Our implementation checks if it is the expected GUID and drops it otherwise.
- see (https://issues.omg.org/issues/DDSIRTP21-4)
* The RTPS Builtin Endpoint skips a Packet it doesn't understand. The RTPS Builtin Endpoint does not parse "serialized key" of DATA messages (since the specification does not actually define what the serialized key even is). So a SPDP DATA Packet with in-line QoS (PID_STATUS_INFO) and serialized key will be dropped if the RTPS Builtin Endpoint does not know the GUID, and that may stall the whole process pipeline (since the SN will be never acknowledged)
* Is the parameter header of an optional member in CDR_LE also endian swapped?
- Yes. (See Figure 24, 7.4.1.2.1, DDS-XTYPES 1.3)
* Based on the examples given in 7.6.8 DDS-XTYPES v1.3 specification it seems that the string bounds do not count the NUL byte.
- Under close inspection the IDL 4.2 specification states under 7.4.1.4.4.3.2
"IDL defines the string type string consisting of a list of all possible 8-bit quantities except null."
Which means that the bound of a bounded string does not count the NUL byte.
* Fast-RTPS does not follow DDSI-RTPS Specification
- Open Github Issue
@ -151,6 +159,9 @@
the BuiltinParticipantMessageReader as if it is configured with RELIABLE_RELIABILITY_QOS.
which means that the default value is 0.
* DDSI-RTPS 2.5 ISSUES
- 8.7.10 Key Hash
Wrong reference 9.6.4.3 (correct 9.6.4.8)
* DDS 1.4 ISSUES
- 2.2.3 Supported QoS
@ -298,16 +309,18 @@ DESIGN DECISIONS
specification, we have to encapsule that code separately and link them as necessary. Two such
dynamic Entities are defined: KEY_HOLDER, and <TYPENAME>_WRAPPER.
The KEY_HOLDER Entity contains a Byte-Wide internal memory (In size equal to the maximum key size),
that can be filled with both PLAIN_CDR/PL_CDR DATA Streams, and PLAIN_CDR/PL_CDR Serialized Key
Streams. The Entity allows outputting the memory contents (Key) either in a KEY_HASH format (needs
that can be filled with PLAIN_CDR/PL_CDR DATA Streams, and Serialized Key Streams.
The Entity allows outputting the memory contents (Key) either in a KEY_HASH format (needs
to instantiate a MD5 calculator), or in Serialized Key Format. The Entity uses the start/opcode/ack
interface for operations (similar to the RTPS/DDS Interface).
The <TYPENAME>_WRAPPER entity has all type-components linked to ports and latched in registers. In
output mode the entity is able to fill the registers with a PLAIN_CDR/PL_CDR Data Stream, and in
input mode the registers are filled directly from the input ports and the Entity is able to produce
a PLAIN_CDR/PL_CDR Data Stream from the registers.
The <TYPENAME>_WRAPPER entity has all type-components linked to ports and latched in registers/memory.
In output mode the entity is able to fill the registers/memory with a PLAIN_CDR/PL_CDR Data Stream, and
in input mode the registers are filled directly from the input ports and the Entity is able to produce
a PLAIN_CDR/PL_CDR Data Stream from the registers/memory.
Due to the type-specific nature of the entities, those are not instantiated inside the DDS Endpoints,
but will be instantiated in a wrapper and linked through port mapping with the DDS Enspoints.
but will be instantiated in a wrapper and linked through port mapping with the DDS Endpoints.
X: Due to port mapping differences between DDS Reader and Writer the <TYPENAME>_WRAPPER is splitt into
<TYPENAME>_READER_WRAPPER and <TYPENAME>_WRITER_WRAPPER.
* Due to the requirements of read_next_instance/take_next_instance of the DDS Reader, the Instances are
inserted in numerical Key Hash order into the Instance Memory. This extra sorting logic is not needed
@ -371,6 +384,12 @@ DESIGN DECISIONS
NOTE: The NOT_ALIVE Samples are always added to the end of the list, not depending on their TS. This
is the only exception in which samples TS does not follow their list order.
* MUTABLE extensibility is currently unsupported, as the PL_CDR encoding needs to be able to dynamically
calculate the sizes of type members, which was deemed to complicated.
* Similar to the previosu decision, only optional members with fixed size are supported (Since the optional
members need a parameter list header, which has a length field).
PROTOCOL UNCOMPLIANCE
=====================
* Partition QoS Not Supported

14
src/Tests/Level_1/L1_Type2_key_holder_test1.vhd
View File

@ -40,13 +40,13 @@ architecture testbench of L1_Type2_key_holder_test1 is
signal TestSequence_TestWChar_w_in : std_logic_vector(CDR_WCHAR_WIDTH-1 downto 0) := (others => '0');
signal TestSequence_TestLongLong_w_in : std_logic_vector(CDR_LONG_LONG_WIDTH-1 downto 0) := (others => '0');
signal TestSequence_TestLongDouble_w_in : std_logic_vector(CDR_LONG_DOUBLE_WIDTH-1 downto 0) := (others => '0');
signal TestSequence_TestLongDouble_valid_w_in : std_logic := '0';
signal TestSequence_TestLongDouble_opt_w_in : std_logic := '0';
signal TestMap_len_in, TestMap_addr_in : std_logic_vector(TESTMAP_ADDR_WIDTH-1 downto 0) := (others => '0');
signal TestMap_ready_in, TestMap_wen_in : std_logic := '0';
signal TestMap_key_w_in : std_logic_vector(CDR_OCTET_WIDTH-1 downto 0) := (others => '0');
signal TestMap_value_w_in : std_logic_vector(CDR_SHORT_WIDTH-1 downto 0) := (others => '0');
signal TestEnum_in : std_logic_vector(TESTENUM_WIDTH-1 downto 0) := (others => '0');
signal TestUnion_valid_in : std_logic := '0';
signal TestUnion_opt_in : std_logic := '0';
signal TestUnion_d_in : std_logic_vector(CDR_CHAR_WIDTH-1 downto 0) := (others => '0');
signal TestUnion_LongU_in : std_logic_vector(CDR_LONG_WIDTH-1 downto 0) := (others => '0');
signal TestUnion_OctetU_in : std_logic_vector(CDR_OCTET_WIDTH-1 downto 0) := (others => '0');
@ -115,8 +115,8 @@ begin
TestSequence_TestLongLong_w => TestSequence_TestLongLong_w_in,
TestSequence_TestLongDouble_r => open,
TestSequence_TestLongDouble_w => TestSequence_TestLongDouble_w_in,
TestSequence_TestLongDouble_valid_r => open,
TestSequence_TestLongDouble_valid_w => TestSequence_TestLongDouble_valid_w_in,
TestSequence_TestLongDouble_opt_r => open,
TestSequence_TestLongDouble_opt_w => TestSequence_TestLongDouble_opt_w_in,
TestMap_len => TestMap_len_in,
TestMap_addr => TestMap_addr_in,
TestMap_ready => TestMap_ready_in,
@ -129,7 +129,7 @@ begin
TestMap_value_r => open,
TestMap_value_w => TestMap_value_w_in,
TestEnum => TestEnum_in,
TestUnion_valid => TestUnion_valid_in,
TestUnion_opt => TestUnion_opt_in,
TestUnion_d => TestUnion_d_in,
TestUnion_LongU => TestUnion_LongU_in,
TestUnion_OctetU => TestUnion_OctetU_in,
@ -204,7 +204,7 @@ begin
-- Static
id_in <= RV.RandSlv(id_in'length);
TestEnum_in <= RV.RandSlv(TestEnum_in'length);
TestUnion_valid_in <= '1';
TestUnion_opt_in <= '1';
TestUnion_d_in <= (others => '0');
TestUnion_LongU_in <= RV.RandSlv(TestUnion_LongU_in'length);
TestUnion_OctetU_in <= RV.RandSlv(TestUnion_OctetU_in'length);
@ -221,7 +221,7 @@ begin
TestSequence_TestWChar_w_in <= RV.RandSlv(TestSequence_TestWChar_w_in'length);
TestSequence_TestLongLong_w_in <= RV.RandSlv(TestSequence_TestLongLong_w_in'length);
TestSequence_TestLongDouble_w_in <= RV.RandSlv(TestSequence_TestLongDouble_w_in'length);
TestSequence_TestLongDouble_valid_w_in <= RV.RandSlv(1)(1);
TestSequence_TestLongDouble_opt_w_in <= RV.RandSlv(1)(1);
for j in 0 to 4 loop
TestSequence_TestArray_addr_in <= int(j,TestSequence_TestArray_addr_in'length);
TestSequence_TestArray_w_in <= RV.RandSlv(TestSequence_TestArray_w_in'length);

14
src/Tests/Level_1/L1_Type2_key_holder_test2.vhd
View File

@ -40,13 +40,13 @@ architecture testbench of L1_Type2_key_holder_test2 is
signal TestSequence_TestWChar_w_in : std_logic_vector(CDR_WCHAR_WIDTH-1 downto 0) := (others => '0');
signal TestSequence_TestLongLong_w_in : std_logic_vector(CDR_LONG_LONG_WIDTH-1 downto 0) := (others => '0');
signal TestSequence_TestLongDouble_w_in : std_logic_vector(CDR_LONG_DOUBLE_WIDTH-1 downto 0) := (others => '0');
signal TestSequence_TestLongDouble_valid_w_in : std_logic := '0';
signal TestSequence_TestLongDouble_opt_w_in : std_logic := '0';
signal TestMap_len_in, TestMap_addr_in : std_logic_vector(TESTMAP_ADDR_WIDTH-1 downto 0) := (others => '0');
signal TestMap_ready_in, TestMap_wen_in : std_logic := '0';
signal TestMap_key_w_in : std_logic_vector(CDR_OCTET_WIDTH-1 downto 0) := (others => '0');
signal TestMap_value_w_in : std_logic_vector(CDR_SHORT_WIDTH-1 downto 0) := (others => '0');
signal TestEnum_in : std_logic_vector(TESTENUM_WIDTH-1 downto 0) := (others => '0');
signal TestUnion_valid_in : std_logic := '0';
signal TestUnion_opt_in : std_logic := '0';
signal TestUnion_d_in : std_logic_vector(CDR_CHAR_WIDTH-1 downto 0) := (others => '0');
signal TestUnion_LongU_in : std_logic_vector(CDR_LONG_WIDTH-1 downto 0) := (others => '0');
signal TestUnion_OctetU_in : std_logic_vector(CDR_OCTET_WIDTH-1 downto 0) := (others => '0');
@ -118,8 +118,8 @@ begin
TestSequence_TestLongLong_w => TestSequence_TestLongLong_w_in,
TestSequence_TestLongDouble_r => open,
TestSequence_TestLongDouble_w => TestSequence_TestLongDouble_w_in,
TestSequence_TestLongDouble_valid_r => open,
TestSequence_TestLongDouble_valid_w => TestSequence_TestLongDouble_valid_w_in,
TestSequence_TestLongDouble_opt_r => open,
TestSequence_TestLongDouble_opt_w => TestSequence_TestLongDouble_opt_w_in,
TestMap_len => TestMap_len_in,
TestMap_addr => TestMap_addr_in,
TestMap_ready => TestMap_ready_in,
@ -132,7 +132,7 @@ begin
TestMap_value_r => open,
TestMap_value_w => TestMap_value_w_in,
TestEnum => TestEnum_in,
TestUnion_valid => TestUnion_valid_in,
TestUnion_opt => TestUnion_opt_in,
TestUnion_d => TestUnion_d_in,
TestUnion_LongU => TestUnion_LongU_in,
TestUnion_OctetU => TestUnion_OctetU_in,
@ -207,7 +207,7 @@ begin
-- Static
id_in <= RV.RandSlv(id_in'length);
TestEnum_in <= RV.RandSlv(TestEnum_in'length);
TestUnion_valid_in <= '1';
TestUnion_opt_in <= '1';
TestUnion_d_in <= (others => '0');
TestUnion_LongU_in <= RV.RandSlv(TestUnion_LongU_in'length);
TestUnion_OctetU_in <= RV.RandSlv(TestUnion_OctetU_in'length);
@ -224,7 +224,7 @@ begin
TestSequence_TestWChar_w_in <= RV.RandSlv(TestSequence_TestWChar_w_in'length);
TestSequence_TestLongLong_w_in <= RV.RandSlv(TestSequence_TestLongLong_w_in'length);
TestSequence_TestLongDouble_w_in <= RV.RandSlv(TestSequence_TestLongDouble_w_in'length);
TestSequence_TestLongDouble_valid_w_in <= RV.RandSlv(1)(1);
TestSequence_TestLongDouble_opt_w_in <= RV.RandSlv(1)(1);
for j in 0 to 4 loop
TestSequence_TestArray_addr_in <= int(j,TestSequence_TestArray_addr_in'length);
TestSequence_TestArray_w_in <= RV.RandSlv(TestSequence_TestArray_w_in'length);

26
src/Tests/Level_1/L1_Type2_wrapper_test1.vhd
View File

@ -35,13 +35,13 @@ architecture testbench of L1_Type2_wrapper_test1 is
signal TestSequence_TestWChar_r_in, TestSequence_TestWChar_w_in, TestSequence_TestWChar_out : std_logic_vector(CDR_WCHAR_WIDTH-1 downto 0) := (others => '0');
signal TestSequence_TestLongLong_r_in, TestSequence_TestLongLong_w_in, TestSequence_TestLongLong_out : std_logic_vector(CDR_LONG_LONG_WIDTH-1 downto 0) := (others => '0');
signal TestSequence_TestLongDouble_r_in, TestSequence_TestLongDouble_w_in, TestSequence_TestLongDouble_out : std_logic_vector(CDR_LONG_DOUBLE_WIDTH-1 downto 0) := (others => '0');
signal TestSequence_TestLongDouble_valid_r_in, TestSequence_TestLongDouble_valid_w_in, TestSequence_TestLongDouble_valid_out : std_logic := '0';
signal TestSequence_TestLongDouble_opt_r_in, TestSequence_TestLongDouble_opt_w_in, TestSequence_TestLongDouble_opt_out : std_logic := '0';
signal TestMap_len_in, TestMap_len_out, TestMap_addr_in, TestMap_addr_out : std_logic_vector(TESTMAP_ADDR_WIDTH-1 downto 0) := (others => '0');
signal TestMap_ready_in, TestMap_ready_out, TestMap_ren_in, TestMap_ren_out, TestMap_wen_in, TestMap_valid_in, TestMap_valid_out, TestMap_ack_in, TestMap_ack_out : std_logic := '0';
signal TestMap_key_r_in, TestMap_key_w_in, TestMap_key_out : std_logic_vector(CDR_OCTET_WIDTH-1 downto 0) := (others => '0');
signal TestMap_value_r_in, TestMap_value_w_in, TestMap_value_out : std_logic_vector(CDR_SHORT_WIDTH-1 downto 0) := (others => '0');
signal TestEnum_in, TestEnum_out : std_logic_vector(TESTENUM_WIDTH-1 downto 0) := (others => '0');
signal TestUnion_valid_in, TestUnion_valid_out : std_logic := '0';
signal TestUnion_opt_in, TestUnion_opt_out : std_logic := '0';
signal TestUnion_d_in, TestUnion_d_out : std_logic_vector(CDR_CHAR_WIDTH-1 downto 0) := (others => '0');
signal TestUnion_LongU_in, TestUnion_LongU_out : std_logic_vector(CDR_LONG_WIDTH-1 downto 0) := (others => '0');
signal TestUnion_OctetU_in, TestUnion_OctetU_out : std_logic_vector(CDR_OCTET_WIDTH-1 downto 0) := (others => '0');
@ -110,8 +110,8 @@ begin
TestSequence_TestLongLong_w => TestSequence_TestLongLong_w_in,
TestSequence_TestLongDouble_r => TestSequence_TestLongDouble_r_in,
TestSequence_TestLongDouble_w => TestSequence_TestLongDouble_w_in,
TestSequence_TestLongDouble_valid_r => TestSequence_TestLongDouble_valid_r_in,
TestSequence_TestLongDouble_valid_w => TestSequence_TestLongDouble_valid_w_in,
TestSequence_TestLongDouble_opt_r => TestSequence_TestLongDouble_opt_r_in,
TestSequence_TestLongDouble_opt_w => TestSequence_TestLongDouble_opt_w_in,
TestMap_len => TestMap_len_in,
TestMap_addr => TestMap_addr_in,
TestMap_ready => TestMap_ready_in,
@ -124,7 +124,7 @@ begin
TestMap_value_r => TestMap_value_r_in,
TestMap_value_w => TestMap_value_w_in,
TestEnum => TestEnum_in,
TestUnion_valid => TestUnion_valid_in,
TestUnion_opt => TestUnion_opt_in,
TestUnion_d => TestUnion_d_in,
TestUnion_LongU => TestUnion_LongU_in,
TestUnion_OctetU => TestUnion_OctetU_in,
@ -220,7 +220,7 @@ begin
TestSequence_TestWChar => TestSequence_TestWChar_out,
TestSequence_TestLongLong => TestSequence_TestLongLong_out,
TestSequence_TestLongDouble => TestSequence_TestLongDouble_out,
TestSequence_TestLongDouble_valid => TestSequence_TestLongDouble_valid_out,
TestSequence_TestLongDouble_opt => TestSequence_TestLongDouble_opt_out,
TestMap_len => TestMap_len_out,
TestMap_addr => TestMap_addr_out,
TestMap_ready => TestMap_ready_out,
@ -230,7 +230,7 @@ begin
TestMap_key => TestMap_key_out,
TestMap_value => TestMap_value_out,
TestEnum => TestEnum_out,
TestUnion_valid => TestUnion_valid_out,
TestUnion_opt => TestUnion_opt_out,
TestUnion_d => TestUnion_d_out,
TestUnion_LongU => TestUnion_LongU_out,
TestUnion_OctetU => TestUnion_OctetU_out,
@ -285,7 +285,7 @@ begin
-- Static
id_in <= RV.RandSlv(id_in'length);
TestEnum_in <= RV.RandSlv(TestEnum_in'length);
TestUnion_valid_in <= '1';
TestUnion_opt_in <= '1';
TestUnion_d_in <= (others => '0');
TestUnion_LongU_in <= RV.RandSlv(TestUnion_LongU_in'length);
TestUnion_OctetU_in <= RV.RandSlv(TestUnion_OctetU_in'length);
@ -299,7 +299,7 @@ begin
TestSequence_TestWChar_w_in <= RV.RandSlv(TestSequence_TestWChar_w_in'length);
TestSequence_TestLongLong_w_in <= RV.RandSlv(TestSequence_TestLongLong_w_in'length);
TestSequence_TestLongDouble_w_in <= RV.RandSlv(TestSequence_TestLongDouble_w_in'length);
TestSequence_TestLongDouble_valid_w_in <= RV.RandSlv(1)(1);
TestSequence_TestLongDouble_opt_w_in <= RV.RandSlv(1)(1);
for j in 0 to 4 loop
TestSequence_TestArray_addr_in <= int(j,TestSequence_TestArray_addr_in'length);
TestSequence_TestArray_w_in <= RV.RandSlv(TestSequence_TestArray_w_in'length);
@ -350,8 +350,8 @@ begin
Log("Compare Writer and Reader Side", INFO);
AffirmIfEqual(ID, id_out, id_in);
AffirmIfEqual(TE, TestEnum_out,TestEnum_in);
AffirmIfEqual(TU, TestUnion_valid_out, TestUnion_valid_in);
if (TestUnion_valid_in = '1') then
AffirmIfEqual(TU, TestUnion_opt_out, TestUnion_opt_in);
if (TestUnion_opt_in = '1') then
AffirmIfEqual(TU, TestUnion_d_out, TestUnion_d_in);
--AffirmIfEqual(TU, TestUnion_LongU_out, TestUnion_LongU_in);
AffirmIfEqual(TU, TestUnion_OctetU_out, TestUnion_OctetU_in);
@ -374,8 +374,8 @@ begin
AffirmIfEqual(TS_TC, TestSequence_TestChar_out, TestSequence_TestChar_r_in);
AffirmIfEqual(TS_TWC, TestSequence_TestWChar_out, TestSequence_TestWChar_r_in);
AffirmIfEqual(TS_TLL, TestSequence_TestLongLong_out, TestSequence_TestLongLong_r_in);
AffirmIfEqual(TS_TLD, TestSequence_TestLongDouble_valid_out, TestSequence_TestLongDouble_valid_r_in);
if (TestSequence_TestLongDouble_valid_r_in = '1') then
AffirmIfEqual(TS_TLD, TestSequence_TestLongDouble_opt_out, TestSequence_TestLongDouble_opt_r_in);
if (TestSequence_TestLongDouble_opt_r_in = '1') then
AffirmIfEqual(TS_TLD, TestSequence_TestLongDouble_out, TestSequence_TestLongDouble_r_in);
end if;
for j in 0 to 4 loop

26
src/Tests/Level_1/L1_Type2_wrapper_test2.vhd
View File

@ -35,13 +35,13 @@ architecture testbench of L1_Type2_wrapper_test2 is
signal TestSequence_TestWChar_r_in, TestSequence_TestWChar_w_in, TestSequence_TestWChar_out : std_logic_vector(CDR_WCHAR_WIDTH-1 downto 0) := (others => '0');
signal TestSequence_TestLongLong_r_in, TestSequence_TestLongLong_w_in, TestSequence_TestLongLong_out : std_logic_vector(CDR_LONG_LONG_WIDTH-1 downto 0) := (others => '0');
signal TestSequence_TestLongDouble_r_in, TestSequence_TestLongDouble_w_in, TestSequence_TestLongDouble_out : std_logic_vector(CDR_LONG_DOUBLE_WIDTH-1 downto 0) := (others => '0');
signal TestSequence_TestLongDouble_valid_r_in, TestSequence_TestLongDouble_valid_w_in, TestSequence_TestLongDouble_valid_out : std_logic := '0';
signal TestSequence_TestLongDouble_opt_r_in, TestSequence_TestLongDouble_opt_w_in, TestSequence_TestLongDouble_opt_out : std_logic := '0';
signal TestMap_len_in, TestMap_len_out, TestMap_addr_in, TestMap_addr_out : std_logic_vector(TESTMAP_ADDR_WIDTH-1 downto 0) := (others => '0');
signal TestMap_ready_in, TestMap_ready_out, TestMap_ren_in, TestMap_ren_out, TestMap_wen_in, TestMap_valid_in, TestMap_valid_out, TestMap_ack_in, TestMap_ack_out : std_logic := '0';
signal TestMap_key_r_in, TestMap_key_w_in, TestMap_key_out : std_logic_vector(CDR_OCTET_WIDTH-1 downto 0) := (others => '0');
signal TestMap_value_r_in, TestMap_value_w_in, TestMap_value_out : std_logic_vector(CDR_SHORT_WIDTH-1 downto 0) := (others => '0');
signal TestEnum_in, TestEnum_out : std_logic_vector(TESTENUM_WIDTH-1 downto 0) := (others => '0');
signal TestUnion_valid_in, TestUnion_valid_out : std_logic := '0';
signal TestUnion_opt_in, TestUnion_opt_out : std_logic := '0';
signal TestUnion_d_in, TestUnion_d_out : std_logic_vector(CDR_CHAR_WIDTH-1 downto 0) := (others => '0');
signal TestUnion_LongU_in, TestUnion_LongU_out : std_logic_vector(CDR_LONG_WIDTH-1 downto 0) := (others => '0');
signal TestUnion_OctetU_in, TestUnion_OctetU_out : std_logic_vector(CDR_OCTET_WIDTH-1 downto 0) := (others => '0');
@ -113,8 +113,8 @@ begin
TestSequence_TestLongLong_w => TestSequence_TestLongLong_w_in,
TestSequence_TestLongDouble_r => TestSequence_TestLongDouble_r_in,
TestSequence_TestLongDouble_w => TestSequence_TestLongDouble_w_in,
TestSequence_TestLongDouble_valid_r => TestSequence_TestLongDouble_valid_r_in,
TestSequence_TestLongDouble_valid_w => TestSequence_TestLongDouble_valid_w_in,
TestSequence_TestLongDouble_opt_r => TestSequence_TestLongDouble_opt_r_in,
TestSequence_TestLongDouble_opt_w => TestSequence_TestLongDouble_opt_w_in,
TestMap_len => TestMap_len_in,
TestMap_addr => TestMap_addr_in,
TestMap_ready => TestMap_ready_in,
@ -127,7 +127,7 @@ begin
TestMap_value_r => TestMap_value_r_in,
TestMap_value_w => TestMap_value_w_in,
TestEnum => TestEnum_in,
TestUnion_valid => TestUnion_valid_in,
TestUnion_opt => TestUnion_opt_in,
TestUnion_d => TestUnion_d_in,
TestUnion_LongU => TestUnion_LongU_in,
TestUnion_OctetU => TestUnion_OctetU_in,
@ -223,7 +223,7 @@ begin
TestSequence_TestWChar => TestSequence_TestWChar_out,
TestSequence_TestLongLong => TestSequence_TestLongLong_out,
TestSequence_TestLongDouble => TestSequence_TestLongDouble_out,
TestSequence_TestLongDouble_valid => TestSequence_TestLongDouble_valid_out,
TestSequence_TestLongDouble_opt => TestSequence_TestLongDouble_opt_out,
TestMap_len => TestMap_len_out,
TestMap_addr => TestMap_addr_out,
TestMap_ready => TestMap_ready_out,
@ -233,7 +233,7 @@ begin
TestMap_key => TestMap_key_out,
TestMap_value => TestMap_value_out,
TestEnum => TestEnum_out,
TestUnion_valid => TestUnion_valid_out,
TestUnion_opt => TestUnion_opt_out,
TestUnion_d => TestUnion_d_out,
TestUnion_LongU => TestUnion_LongU_out,
TestUnion_OctetU => TestUnion_OctetU_out,
@ -288,7 +288,7 @@ begin
-- Static
id_in <= RV.RandSlv(id_in'length);
TestEnum_in <= RV.RandSlv(TestEnum_in'length);
TestUnion_valid_in <= '1';
TestUnion_opt_in <= '1';
TestUnion_d_in <= (others => '0');
TestUnion_LongU_in <= RV.RandSlv(TestUnion_LongU_in'length);
TestUnion_OctetU_in <= RV.RandSlv(TestUnion_OctetU_in'length);
@ -302,7 +302,7 @@ begin
TestSequence_TestWChar_w_in <= RV.RandSlv(TestSequence_TestWChar_w_in'length);
TestSequence_TestLongLong_w_in <= RV.RandSlv(TestSequence_TestLongLong_w_in'length);
TestSequence_TestLongDouble_w_in <= RV.RandSlv(TestSequence_TestLongDouble_w_in'length);
TestSequence_TestLongDouble_valid_w_in <= RV.RandSlv(1)(1);
TestSequence_TestLongDouble_opt_w_in <= RV.RandSlv(1)(1);
for j in 0 to 4 loop
TestSequence_TestArray_addr_in <= int(j,TestSequence_TestArray_addr_in'length);
TestSequence_TestArray_w_in <= RV.RandSlv(TestSequence_TestArray_w_in'length);
@ -353,8 +353,8 @@ begin
Log("Compare Writer and Reader Side", INFO);
AffirmIfEqual(ID, id_out, id_in);
AffirmIfEqual(TE, TestEnum_out,TestEnum_in);
AffirmIfEqual(TU, TestUnion_valid_out, TestUnion_valid_in);
if (TestUnion_valid_in = '1') then
AffirmIfEqual(TU, TestUnion_opt_out, TestUnion_opt_in);
if (TestUnion_opt_in = '1') then
AffirmIfEqual(TU, TestUnion_d_out, TestUnion_d_in);
--AffirmIfEqual(TU, TestUnion_LongU_out, TestUnion_LongU_in);
AffirmIfEqual(TU, TestUnion_OctetU_out, TestUnion_OctetU_in);
@ -377,8 +377,8 @@ begin
AffirmIfEqual(TS_TC, TestSequence_TestChar_out, TestSequence_TestChar_r_in);
AffirmIfEqual(TS_TWC, TestSequence_TestWChar_out, TestSequence_TestWChar_r_in);
AffirmIfEqual(TS_TLL, TestSequence_TestLongLong_out, TestSequence_TestLongLong_r_in);
AffirmIfEqual(TS_TLD, TestSequence_TestLongDouble_valid_out, TestSequence_TestLongDouble_valid_r_in);
if (TestSequence_TestLongDouble_valid_r_in = '1') then
AffirmIfEqual(TS_TLD, TestSequence_TestLongDouble_opt_out, TestSequence_TestLongDouble_opt_r_in);
if (TestSequence_TestLongDouble_opt_r_in = '1') then
AffirmIfEqual(TS_TLD, TestSequence_TestLongDouble_out, TestSequence_TestLongDouble_r_in);
end if;
for j in 0 to 4 loop

91
src/Tests/Type2_key_holder.vhd
View File

@ -9,7 +9,7 @@ use work.Type2_package.all;
architecture TYPE2 of key_holder is
--*****COMPONENT DECLARATION*****
component md5_calculator is
component key_hash_generator is
port (
clk : in std_logic;
reset : in std_logic;
@ -22,14 +22,14 @@ architecture TYPE2 of key_holder is
ready_in : out std_logic;
last_word_in : in std_logic;
hash_out : out std_logic_vector(127 downto 0);
key_hash : out std_logic_vector(127 downto 0);
done : out std_logic
);
end component;
--*****TYPE DECLARATION*****
-- FSM states. Explained below in detail
type STAGE_TYPE is (IDLE,START_MD5_CALCULATION,GET_PAYLOAD_HEADER,FETCH,ALIGN_IN_STREAM,SKIP_PAYLOAD,DECODE_PAYLOAD,PUSH,ALIGN_OUT_STREAM,SERIALIZE_KEY,GET_KEY_HASH,PUSH_KEY_HASH);
type STAGE_TYPE is (IDLE,START_KEY_HASH_GENERATION,GET_PAYLOAD_HEADER,FETCH,ALIGN_IN_STREAM,SKIP_PAYLOAD,DECODE_PAYLOAD,PUSH,ALIGN_OUT_STREAM,SERIALIZE_KEY,GET_KEY_HASH,PUSH_KEY_HASH);
-- ###GENERATED START###
type DECODE_STAGE_TYPE is (GET_ID,GET_TESTSEQUENCE_LENGTH,GET_TESTSEQUENCE_TESTARRAY,GET_TESTSEQUENCE_TESTCHAR,GET_TESTSEQUENCE_TESTWCHAR,GET_TESTSEQUENCE_TESTLONGLONG,GET_TESTSEQUENCE_TESTLONGDOUBLE,TESTSEQUENCE_MEMBER_END,GET_OPTIONAL_HEADER);
type ENCODE_STAGE_TYPE is (WRITE_ID,WRITE_TESTSEQUENCE_LENGTH,WRITE_TESTSEQUENCE_TESTARRAY,TESTSEQUENCE_MEMBER_END);
@ -54,15 +54,15 @@ architecture TYPE2 of key_holder is
signal align_op, align_op_next : std_logic := '0';
signal finalize_payload, finalize_payload_next : std_logic := '0';
signal ready_in_sig : std_logic := '0';
-- ###GENERATED START###
signal start_md5, ack_md5, done_md5 : std_logic := '0';
signal data_in_md5 : std_logic_vector(BYTE_WIDTH-1 downto 0) := (others => '0');
signal valid_in_md5, ready_in_md5, last_word_in_md5 : std_logic := '0';
signal hash_out_md5 : std_logic_vector(KEY_HASH_WIDTH-1 downto 0) := (others => '0');
signal start_kh, ack_kh, done_kh : std_logic := '0';
signal data_in_kh : std_logic_vector(BYTE_WIDTH-1 downto 0) := (others => '0');
signal valid_in_kh, ready_in_kh, last_word_in_kh : std_logic := '0';
signal key_hash_kh : std_logic_vector(KEY_HASH_WIDTH-1 downto 0) := (others => '0');
signal key_hash, key_hash_next : KEY_HASH_TYPE := HANDLE_NIL;
signal decode_stage, decode_stage_next : DECODE_STAGE_TYPE := GET_ID;
signal encode_stage, encode_stage_next : ENCODE_STAGE_TYPE := WRITE_ID;
signal return_stage, return_stage_next : DECODE_STAGE_TYPE := GET_ID;
-- ###GENERATED START###
signal id_latch, id_latch_next : std_logic_vector(CDR_LONG_WIDTH-1 downto 0) := (others => '0');
signal TestSequence_cnt, TestSequence_cnt_next : natural range 0 to TESTSEQUENCE_MAX_DEPTH-1 := 0;
signal TestSequence_len_latch, TestSequence_len_latch_next : unsigned(TESTSEQUENCE_ADDR_WIDTH-1 downto 0) := (others => '0');
@ -83,6 +83,20 @@ architecture TYPE2 of key_holder is
begin
key_hash_generator_inst : key_hash_generator
port map (
clk => clk,
reset => reset,
start => start_kh,
ack => ack_kh,
data_in => data_in_kh,
valid_in => valid_in_kh,
ready_in => ready_in_kh,
last_word_in => last_word_in_kh,
key_hash => key_hash_kh,
done => done_kh
);
-- ###GENERATED START###
TestSequence_TestArray_gen : for i in 0 to TESTSEQUENCE_MAX_DEPTH-1 generate
begin
@ -106,20 +120,6 @@ begin
data_out => TestSequence_TestArray_mem_data_out(i)
);
end generate;
md5_calculator_inst : md5_calculator
port map (
clk => clk,
reset => reset,
start => start_md5,
ack => ack_md5,
data_in => data_in_md5,
valid_in => valid_in_md5,
ready_in => ready_in_md5,
last_word_in => last_word_in_md5,
hash_out => hash_out_md5,
done => done_md5
);
-- ###GENERATED END###
decode_error <= decode_error_latch;
@ -152,9 +152,9 @@ begin
ready_in_sig <= '0';
last_word_out <= '0';
valid_out <= '0';
start_md5 <= '0';
valid_in_md5 <= '0';
data_in_md5 <= (others => '0');
start_kh <= '0';
valid_in_kh <= '0';
data_in_kh <= (others => '0');
data_out <= (others => '0');
-- ###GENERATED START###
id_latch_next <= id_latch;
@ -191,15 +191,17 @@ begin
-- Serialized Key is in PLAIN_CDR2 Big Endian encoding
endian_flag_next <= '0';
stage_next <= FETCH;
decode_stage_next <= GET_ID;
-- Alignment Reset
align_offset_next <= (others => '0');
-- ###GENERATED START###
decode_stage_next <= GET_ID;
-- ###GENERATED END###
when READ_KEY_HASH =>
ack <= '1';
-- Key Hash not calculated
if (key_hash = HANDLE_NIL) then
-- DES: If MAX_TYPE2_KEY_HOLDER_SIZE is <= 16 we don't have to calculate the md5 (or even instantiate the md5_calculator at all)
stage_next <= START_MD5_CALCULATION;
stage_next <= START_KEY_HASH_GENERATION;
else
stage_next <= PUSH_KEY_HASH;
cnt_next <= 0;
@ -207,18 +209,20 @@ begin
when READ_SERIALIZED_KEY =>
ack <= '1';
stage_next <= SERIALIZE_KEY;
encode_stage_next <= WRITE_ID;
-- Alignment Reset
align_offset_next <= (others => '0');
data_out_latch_next <= (others => '0');
-- ###GENERATED START###
encode_stage_next <= WRITE_ID;
-- ###GENERATED END###
when others =>
null;
end case;
end if;
when START_MD5_CALCULATION =>
start_md5 <= '1';
when START_KEY_HASH_GENERATION =>
start_kh <= '1';
if (ack_md5 = '1') then
if (ack_kh = '1') then
stage_next <= SERIALIZE_KEY;
encode_stage_next <= WRITE_ID;
end if;
@ -232,16 +236,19 @@ begin
when CDR_BE =>
endian_flag_next <= '0';
stage_next <= FETCH;
decode_stage_next <= GET_ID;
-- Alignment Reset
align_offset_next <= (others => '0');
-- Initial Fetch
-- ###GENERATED START###
decode_stage_next <= GET_ID;
-- ###GENERATED END###
when CDR_LE =>
endian_flag_next <= '1';
stage_next <= FETCH;
decode_stage_next <= GET_ID;
-- Alignment Reset
align_offset_next <= (others => '0');
-- ###GENERATED START###
decode_stage_next <= GET_ID;
-- ###GENERATED END###
when others =>
-- Unknown Payload Encoding
stage_next <= SKIP_PAYLOAD;
@ -510,17 +517,17 @@ begin
end case;
-- ###GENERATED END###
when PUSH =>
-- Push to MD5 Calculator
-- Push to Key Hash Generator
if (opcode_latch = READ_KEY_HASH) then
-- Mark Last Word
if (finalize_payload = '1' and cnt_2 = to_integer(unsigned(align_offset(1 downto 0)))) then
last_word_in_md5 <= '1';
last_word_in_kh <= '1';
end if;
valid_in_md5 <= '1';
data_in_md5 <= get_sub_vector(data_out_latch, cnt_2, BYTE_WIDTH, TRUE);
valid_in_kh <= '1';
data_in_kh <= get_sub_vector(data_out_latch, cnt_2, BYTE_WIDTH, TRUE);
-- Output Guard
if (ready_in_md5 = '1') then
if (ready_in_kh = '1') then
-- Last Byte
if ((finalize_payload = '1' and cnt_2 = to_integer(unsigned(align_offset(1 downto 0)))) or cnt_2 = (WORD_WIDTH/BYTE_WIDTH)-1) then
-- Reset
@ -676,8 +683,8 @@ begin
end case;
-- ###GENERATED END###
when GET_KEY_HASH =>
if (done_md5 = '1') then
key_hash_next <= to_key_hash(hash_out_md5);
if (done_kh = '1') then
key_hash_next <= to_key_hash(key_hash_kh);
stage_next <= PUSH_KEY_HASH;
cnt_next <= 0;
end if;

165
src/Tests/Type2_reader_wrapper.vhd
View File

@ -96,7 +96,7 @@ entity Type2_reader_wrapper is
TestSequence_TestWChar : out std_logic_vector(CDR_WCHAR_WIDTH-1 downto 0);
TestSequence_TestLongLong : out std_logic_vector(CDR_LONG_LONG_WIDTH-1 downto 0);
TestSequence_TestLongDouble : out std_logic_vector(CDR_LONG_DOUBLE_WIDTH-1 downto 0);
TestSequence_TestLongDouble_valid : out std_logic;
TestSequence_TestLongDouble_opt : out std_logic;
TestMap_len : out std_logic_vector(TESTMAP_ADDR_WIDTH-1 downto 0);
TestMap_addr : in std_logic_vector(TESTMAP_ADDR_WIDTH-1 downto 0);
TestMap_ready : out std_logic;
@ -106,7 +106,7 @@ entity Type2_reader_wrapper is
TestMap_key : out std_logic_vector(CDR_OCTET_WIDTH-1 downto 0);
TestMap_value : out std_logic_vector(CDR_SHORT_WIDTH-1 downto 0);
TestEnum : out std_logic_vector(TESTENUM_WIDTH-1 downto 0);
TestUnion_valid : out std_logic;
TestUnion_opt : out std_logic;
TestUnion_d : out std_logic_vector(CDR_CHAR_WIDTH-1 downto 0);
TestUnion_LongU : out std_logic_vector(CDR_LONG_WIDTH-1 downto 0);
TestUnion_OctetU : out std_logic_vector(CDR_OCTET_WIDTH-1 downto 0);
@ -159,11 +159,10 @@ architecture arch of Type2_reader_wrapper is
signal TestSequence_TestArray_cnt, TestSequence_TestArray_cnt_next : natural range 0 to TESTSEQUENCE_TESTARRAY_MAX_DEPTH-1 := 0;
signal TestMap_cnt, TestMap_cnt_next : natural range 0 to TESTMAP_MAX_DEPTH-1 := 0;
signal TestMap_len_latch, TestMap_len_latch_next : unsigned(TESTMAP_ADDR_WIDTH-1 downto 0) := (others => '0');
signal TestMap_key_latch, TestMap_key_latch_next : std_logic_vector(CDR_OCTET_WIDTH-1 downto 0) := (others => '0');
signal TestString_cnt, TestString_cnt_next : natural range 0 to TESTSTRING_MAX_DEPTH-1 := 0;
signal TestString_len_latch, TestString_len_latch_next : unsigned(TESTSTRING_ADDR_WIDTH-1 downto 0) := (others => '0');
signal TestEnum_latch, TestEnum_latch_next : std_logic_vector(TESTENUM_WIDTH-1 downto 0) := (others => '0');
signal TestUnion_valid_latch, TestUnion_valid_latch_next : std_logic := '0';
signal TestUnion_opt_latch, TestUnion_opt_latch_next : std_logic := '0';
signal TestUnion_d_latch, TestUnion_d_latch_next : std_logic_vector(CDR_CHAR_WIDTH-1 downto 0) := (others => '0');
signal TestUnion_LongU_latch, TestUnion_LongU_latch_next : std_logic_vector(CDR_LONG_WIDTH-1 downto 0) := (others => '0');
signal TestUnion_OctetU_latch, TestUnion_OctetU_latch_next : std_logic_vector(CDR_OCTET_WIDTH-1 downto 0) := (others => '0');
@ -188,10 +187,14 @@ architecture arch of Type2_reader_wrapper is
signal TestSequence_TestArray_mem_addr : TESTSEQUENCE_TESTARRAY_ADDR_TYPE := (others => (others => '0'));
signal TestSequence_TestArray_mem_read, TestSequence_TestArray_mem_ready_in, TestSequence_TestArray_mem_ready_out, TestSequence_TestArray_mem_valid_in, TestSequence_TestArray_mem_valid_out : std_logic_vector(0 to TESTSEQUENCE_TESTARRAY_MAX_DEPTH-1) := (others => '0');
signal TestSequence_TestArray_mem_data_in, TestSequence_TestArray_mem_data_out : TESTSEQUENCE_TESTARRAY_DATA_TYPE := (others => (others => '0'));
-- TestMap_mem SIGNALS
signal TestMap_mem_addr : std_logic_vector(TESTMAP_ADDR_WIDTH-1 downto 0) := (others => '0');
signal TestMap_mem_read, TestMap_mem_ready_in, TestMap_mem_ready_out, TestMap_mem_valid_in, TestMap_mem_valid_out : std_logic := '0';
signal TestMap_mem_data_in, TestMap_mem_data_out : std_logic_vector(CDR_OCTET_WIDTH+CDR_SHORT_WIDTH-1 downto 0) := (others => '0');
-- TestMap_key_mem SIGNALS
signal TestMap_key_mem_addr : std_logic_vector(TESTMAP_ADDR_WIDTH-1 downto 0) := (others => '0');
signal TestMap_key_mem_read, TestMap_key_mem_ready_in, TestMap_key_mem_ready_out, TestMap_key_mem_valid_in, TestMap_key_mem_valid_out : std_logic := '0';
signal TestMap_key_mem_data_in, TestMap_key_mem_data_out : std_logic_vector(CDR_OCTET_WIDTH-1 downto 0) := (others => '0');
-- TestMap_value_mem SIGNALS
signal TestMap_value_mem_addr : std_logic_vector(TESTMAP_ADDR_WIDTH-1 downto 0) := (others => '0');
signal TestMap_value_mem_read, TestMap_value_mem_ready_in, TestMap_value_mem_ready_out, TestMap_value_mem_valid_in, TestMap_value_mem_valid_out : std_logic := '0';
signal TestMap_value_mem_data_in, TestMap_value_mem_data_out : std_logic_vector(CDR_SHORT_WIDTH-1 downto 0) := (others => '0');
-- TestString_mem SIGNALS
signal TestString_mem_addr : std_logic_vector(TESTSTRING_ADDR_WIDTH-1 downto 0) := (others => '0');
signal TestString_mem_read, TestString_mem_ready_in, TestString_mem_ready_out, TestString_mem_valid_in, TestString_mem_valid_out : std_logic := '0';
@ -311,24 +314,44 @@ begin
);
end generate;
TestMap_mem : entity work.mem_ctrl(arch)
TestMap_key_mem : entity work.mem_ctrl(arch)
generic map (
ADDR_WIDTH => TESTMAP_ADDR_WIDTH,
DATA_WIDTH => CDR_OCTET_WIDTH+CDR_SHORT_WIDTH,
DATA_WIDTH => CDR_OCTET_WIDTH,
MEMORY_DEPTH => TESTMAP_MAX_DEPTH,
MAX_BURST_LENGTH => 1
)
port map (
clk => clk,
reset => reset or abort_mem,
addr => TestMap_mem_addr,
read => TestMap_mem_read,
ready_in => TestMap_mem_ready_in,
valid_in => TestMap_mem_valid_in,
data_in => TestMap_mem_data_in,
ready_out => TestMap_mem_ready_out,
valid_out => TestMap_mem_valid_out,
data_out => TestMap_mem_data_out
addr => TestMap_key_mem_addr,
read => TestMap_key_mem_read,
ready_in => TestMap_key_mem_ready_in,
valid_in => TestMap_key_mem_valid_in,
data_in => TestMap_key_mem_data_in,
ready_out => TestMap_key_mem_ready_out,
valid_out => TestMap_key_mem_valid_out,
data_out => TestMap_key_mem_data_out
);
TestMap_value_mem : entity work.mem_ctrl(arch)
generic map (
ADDR_WIDTH => TESTMAP_ADDR_WIDTH,
DATA_WIDTH => CDR_SHORT_WIDTH,
MEMORY_DEPTH => TESTMAP_MAX_DEPTH,
MAX_BURST_LENGTH => 1
)
port map (
clk => clk,
reset => reset or abort_mem,
addr => TestMap_value_mem_addr,
read => TestMap_value_mem_read,
ready_in => TestMap_value_mem_ready_in,
valid_in => TestMap_value_mem_valid_in,
data_in => TestMap_value_mem_data_in,
ready_out => TestMap_value_mem_ready_out,
valid_out => TestMap_value_mem_valid_out,
data_out => TestMap_value_mem_data_out
);
TestString_mem : entity work.mem_ctrl(arch)
@ -397,13 +420,13 @@ begin
TestSequence_TestWChar <= TestSequence_TestWChar_mem_data_out;
TestSequence_TestLongLong <= TestSequence_TestLongLong_mem_data_out;
TestSequence_TestLongDouble <= TestSequence_TestLongDouble_mem_data_out(CDR_LONG_DOUBLE_WIDTH-1 downto 0);
TestSequence_TestLongDouble_valid <= TestSequence_TestLongDouble_mem_data_out(CDR_LONG_DOUBLE_WIDTH);
TestSequence_TestLongDouble_opt <= TestSequence_TestLongDouble_mem_data_out(CDR_LONG_DOUBLE_WIDTH);
TestMap_len <= std_logic_vector(TestMap_len_latch);
TestMap_valid <= TestMap_mem_valid_out;
TestMap_key <= TestMap_mem_data_out(CDR_OCTET_WIDTH+CDR_SHORT_WIDTH-1 downto CDR_SHORT_WIDTH);
TestMap_value <= TestMap_mem_data_out(CDR_SHORT_WIDTH-1 downto 0);
TestMap_valid <= TestMap_key_mem_valid_out and TestMap_value_mem_valid_out;
TestMap_key <= TestMap_key_mem_data_out;
TestMap_value <= TestMap_value_mem_data_out;
TestEnum <= TestEnum_latch;
TestUnion_valid <= TestUnion_valid_latch;
TestUnion_opt <= TestUnion_opt_latch;
TestUnion_d <= TestUnion_d_latch;
TestUnion_LongU <= TestUnion_LongU_latch;
TestUnion_OctetU <= TestUnion_OctetU_latch;
@ -418,7 +441,7 @@ begin
begin
-- DEFAULT
stage_next <= stage;
decode_stage_next <= decode_stage;
decode_stage_next <= decode_stage;
return_stage_next <= return_stage;
cnt_next <= cnt;
endian_flag_next <= endian_flag;
@ -429,12 +452,12 @@ begin
optional_next <= optional;
valid_latch_next <= valid_latch;
data_in_latch_next <= data_in_latch;
dw_latch_next <= dw_latch;
qw_latch_next <= qw_latch;
align_op_next <= align_op;
abort_mem <= '0';
ready_in_dds_sig <= '0';
-- ###GENERATED START###
dw_latch_next <= dw_latch;
qw_latch_next <= qw_latch;
id_latch_next <= id_latch;
TestSequence_len_latch_next <= TestSequence_len_latch;
TestSequence_cnt_next <= TestSequence_cnt;
@ -442,9 +465,8 @@ begin
TestSequence_addr_latch_next <= TestSequence_addr_latch;
TestMap_cnt_next <= TestMap_cnt;
TestMap_len_latch_next <= TestMap_len_latch;
TestMap_key_latch_next <= TestMap_key_latch;
TestEnum_latch_next <= TestEnum_latch;
TestUnion_valid_latch_next <= TestUnion_valid_latch;
TestUnion_opt_latch_next <= TestUnion_opt_latch;
TestUnion_d_latch_next <= TestUnion_d_latch;
TestUnion_LongU_latch_next <= TestUnion_LongU_latch;
TestUnion_OctetU_latch_next <= TestUnion_OctetU_latch;
@ -476,11 +498,16 @@ begin
TestSequence_TestArray_mem_valid_in <= (others => '0');
TestSequence_TestArray_mem_ready_out <= (others => '0');
TestSequence_TestArray_mem_data_in <= (others => (others => '0'));
TestMap_mem_addr <= (others => '0');
TestMap_mem_read <= '0';
TestMap_mem_valid_in <= '0';
TestMap_mem_ready_out <= '0';
TestMap_mem_data_in <= (others => '0');
TestMap_key_mem_addr <= (others => '0');
TestMap_key_mem_read <= '0';
TestMap_key_mem_valid_in <= '0';
TestMap_key_mem_ready_out <= '0';
TestMap_key_mem_data_in <= (others => '0');
TestMap_value_mem_addr <= (others => '0');
TestMap_value_mem_read <= '0';
TestMap_value_mem_valid_in <= '0';
TestMap_value_mem_ready_out <= '0';
TestMap_value_mem_data_in <= (others => '0');
TestString_mem_addr <= (others => '0');
TestString_mem_read <= '0';
TestString_mem_valid_in <= '0';
@ -507,6 +534,7 @@ begin
valid_latch_next <= '0';
abort_mem <= '1';
else
-- ###GENERATED START###
TestSequence_ready <= TestSequence_TestChar_mem_ready_in and TestSequence_TestWChar_mem_ready_in and TestSequence_TestLongLong_mem_ready_in and TestSequence_TestLongDouble_mem_ready_in;
TestSequence_TestChar_mem_addr <= TestSequence_addr;
TestSequence_TestChar_mem_read <= TestSequence_ren;
@ -533,16 +561,21 @@ begin
if (TestSequence_TestArray_ren = '1') then
TestSequence_addr_latch_next <= TestSequence_addr;
end if;
TestMap_ready <= TestMap_mem_ready_in;
TestMap_mem_addr <= TestMap_addr;
TestMap_mem_read <= TestMap_ren;
TestMap_mem_valid_in <= TestMap_ren;
TestMap_mem_ready_out <= TestMap_ack;
TestMap_ready <= TestMap_key_mem_ready_in and TestMap_value_mem_ready_in;
TestMap_key_mem_addr <= TestMap_addr;
TestMap_key_mem_read <= TestMap_ren;
TestMap_key_mem_valid_in <= TestMap_ren;
TestMap_key_mem_ready_out <= TestMap_ack;
TestMap_value_mem_addr <= TestMap_addr;
TestMap_value_mem_read <= TestMap_ren;
TestMap_value_mem_valid_in <= TestMap_ren;
TestMap_value_mem_ready_out <= TestMap_ack;
TestString_ready <= TestString_mem_ready_in;
TestString_mem_addr <= TestString_addr;
TestString_mem_read <= TestString_ren;
TestString_mem_valid_in <= TestString_ren;
TestString_mem_ready_out <= TestString_ack;
-- ###GENERATED END###
end if;
when GET_PAYLOAD_HEADER =>
-- TODO: Latch Offset from Options Field?
@ -554,16 +587,20 @@ begin
when CDR_BE =>
endian_flag_next <= '0';
stage_next <= FETCH;
decode_stage_next <= GET_ID;
-- Alignment Reset
align_offset_next <= (others => '0');
-- ###GENERATED START###
decode_stage_next <= GET_ID;
-- ###GENERATED END###
-- Initial Fetch
when CDR_LE =>
endian_flag_next <= '1';
stage_next <= FETCH;
decode_stage_next <= GET_ID;
-- Alignment Reset
align_offset_next <= (others => '0');
-- ###GENERATED START###
decode_stage_next <= GET_ID;
-- ###GENERATED END###
when others =>
-- Unknown Payload Encoding
stage_next <= SKIP_PAYLOAD;
@ -613,8 +650,8 @@ begin
last_word_in_latch_next <= '0';
end if;
when DECODE_PAYLOAD =>
-- ###GENERATED START###
case (decode_stage) is
-- ###GENERATED START###
when GET_ID =>
-- ALIGN GUARD
if (not check_align(align_offset, ALIGN_4)) then
@ -843,13 +880,19 @@ begin
target_align_next <= ALIGN_1;
stage_next <= ALIGN_STREAM;
else
TestMap_key_latch_next <= endian_swap(endian_flag, get_sub_vector(data_in_latch, to_integer(align_offset(1 downto 0)), CDR_OCTET_WIDTH, TRUE));
align_offset_next <= align_offset + 1;
decode_stage_next <= GET_TESTMAP_VALUE;
TestMap_key_mem_addr <= std_logic_vector(to_unsigned(TestMap_cnt,TESTMAP_ADDR_WIDTH));
TestMap_key_mem_data_in <= endian_swap(endian_flag, get_sub_vector(data_in_latch, to_integer(align_offset(1 downto 0)), CDR_OCTET_WIDTH, TRUE));
TestMap_key_mem_valid_in <= '1';
-- Need to fetch next Word
if(align_offset(1 downto 0) = "11") then
stage_next <= FETCH;
-- Memory Operation Guard
if (TestMap_key_mem_ready_in = '1') then
align_offset_next <= align_offset + 1;
decode_stage_next <= GET_TESTMAP_VALUE;
-- Need to fetch next Word
if(align_offset(1 downto 0) = "11") then
stage_next <= FETCH;
end if;
end if;
end if;
when GET_TESTMAP_VALUE =>
@ -858,14 +901,14 @@ begin
target_align_next <= ALIGN_2;
stage_next <= ALIGN_STREAM;
else
TestMap_mem_addr <= std_logic_vector(to_unsigned(TestMap_cnt,TESTMAP_ADDR_WIDTH));
TestMap_mem_data_in <= TestMap_key_latch & endian_swap(endian_flag, get_sub_vector(data_in_latch, to_integer(align_offset(1 downto 1)), CDR_SHORT_WIDTH, TRUE));
TestMap_mem_valid_in <= '1';
TestMap_value_mem_addr <= std_logic_vector(to_unsigned(TestMap_cnt,TESTMAP_ADDR_WIDTH));
TestMap_value_mem_data_in <= endian_swap(endian_flag, get_sub_vector(data_in_latch, to_integer(align_offset(1 downto 1)), CDR_SHORT_WIDTH, TRUE));
TestMap_value_mem_valid_in <= '1';
-- Memory Operation Guard
if (TestMap_mem_ready_in = '1') then
if (TestMap_value_mem_ready_in = '1') then
align_offset_next <= align_offset + 2;
decode_stage_next <= TESTMAP_MEMBER_END;
decode_stage_next <= TESTMAP_MEMBER_END;
-- Need to fetch next Word
if(align_offset(1 downto 1) = "1") then
@ -904,7 +947,7 @@ begin
-- Optional Omitted
if (optional = '0') then
decode_stage_next <= GET_TESTBITMASK;
TestUnion_valid_latch_next <= '0';
TestUnion_opt_latch_next <= '0';
-- ALIGN GUARD
elsif (not check_align(align_offset, ALIGN_1)) then
target_align_next <= ALIGN_1;
@ -912,14 +955,14 @@ begin
else
align_offset_next <= align_offset + 1;
TestUnion_valid_latch_next <= '1';
TestUnion_opt_latch_next <= '1';
TestUnion_d_latch_next <= endian_swap(endian_flag, get_sub_vector(data_in_latch, to_integer(align_offset(1 downto 0)), CDR_CHAR_WIDTH, TRUE));
case (endian_swap(endian_flag, get_sub_vector(data_in_latch, to_integer(align_offset(1 downto 0)), CDR_CHAR_WIDTH, TRUE))) is
when TESTUNION_LONGU_D =>
decode_stage_next <= GET_TESTUNION_LONGU;
decode_stage_next <= GET_TESTUNION_LONGU;
when others =>
decode_stage_next <= GET_TESTUNION_OCTETU;
decode_stage_next <= GET_TESTUNION_OCTETU;
end case;
-- Need to fetch next Word
@ -988,7 +1031,7 @@ begin
else
TestString_len_latch_next <= resize(tmp_length, TestString_len_latch_next'length);
TestString_cnt_next <= 0;
decode_stage_next <= GET_TESTSTRING;
decode_stage_next <= GET_TESTSTRING;
end if;
end if;
when GET_TESTSTRING =>
@ -1018,6 +1061,7 @@ begin
end if;
end if;
end if;
-- ###GENERATED END###
when GET_OPTIONAL_HEADER =>
-- ALIGN GUARD
if (not check_align(align_offset, ALIGN_4)) then
@ -1071,7 +1115,6 @@ begin
when others =>
null;
end case;
-- ###GENERATED END###
when others =>
null;
end case;
@ -1112,9 +1155,8 @@ begin
TestSequence_addr_latch <= (others => '0');
TestMap_cnt <= 0;
TestMap_len_latch <= (others => '0');
TestMap_key_latch <= (others => '0');
TestEnum_latch <= (others => '0');
TestUnion_valid_latch <= '0';
TestUnion_opt_latch <= '0';
TestUnion_d_latch <= (others => '0');
TestUnion_LongU_latch <= (others => '0');
TestUnion_OctetU_latch <= (others => '0');
@ -1146,9 +1188,8 @@ begin
TestSequence_addr_latch <= TestSequence_addr_latch_next;
TestMap_cnt <= TestMap_cnt_next;
TestMap_len_latch <= TestMap_len_latch_next;
TestMap_key_latch <= TestMap_key_latch_next;
TestEnum_latch <= TestEnum_latch_next;
TestUnion_valid_latch <= TestUnion_valid_latch_next;
TestUnion_opt_latch <= TestUnion_opt_latch_next;
TestUnion_d_latch <= TestUnion_d_latch_next;
TestUnion_LongU_latch <= TestUnion_LongU_latch_next;
TestUnion_OctetU_latch <= TestUnion_OctetU_latch_next;

158
src/Tests/Type2_writer_wrapper.vhd
View File

@ -76,8 +76,8 @@ entity Type2_writer_wrapper is
TestSequence_TestLongLong_w : in std_logic_vector(CDR_LONG_LONG_WIDTH-1 downto 0);
TestSequence_TestLongDouble_r : out std_logic_vector(CDR_LONG_DOUBLE_WIDTH-1 downto 0);
TestSequence_TestLongDouble_w : in std_logic_vector(CDR_LONG_DOUBLE_WIDTH-1 downto 0);
TestSequence_TestLongDouble_valid_r : out std_logic;
TestSequence_TestLongDouble_valid_w : in std_logic;
TestSequence_TestLongDouble_opt_r : out std_logic;
TestSequence_TestLongDouble_opt_w : in std_logic;
TestMap_len : in std_logic_vector(TESTMAP_ADDR_WIDTH-1 downto 0);
TestMap_addr : in std_logic_vector(TESTMAP_ADDR_WIDTH-1 downto 0);
TestMap_ready : out std_logic;
@ -90,7 +90,7 @@ entity Type2_writer_wrapper is
TestMap_value_r : out std_logic_vector(CDR_SHORT_WIDTH-1 downto 0);
TestMap_value_w : in std_logic_vector(CDR_SHORT_WIDTH-1 downto 0);
TestEnum : in std_logic_vector(TESTENUM_WIDTH-1 downto 0);
TestUnion_valid : in std_logic;
TestUnion_opt : in std_logic;
TestUnion_d : in std_logic_vector(CDR_CHAR_WIDTH-1 downto 0);
TestUnion_LongU : in std_logic_vector(CDR_LONG_WIDTH-1 downto 0);
TestUnion_OctetU : in std_logic_vector(CDR_OCTET_WIDTH-1 downto 0);
@ -154,10 +154,14 @@ architecture arch of Type2_writer_wrapper is
signal TestSequence_TestArray_mem_addr : TESTSEQUENCE_TESTARRAY_ADDR_TYPE := (others => (others => '0'));
signal TestSequence_TestArray_mem_read, TestSequence_TestArray_mem_ready_in, TestSequence_TestArray_mem_ready_out, TestSequence_TestArray_mem_valid_in, TestSequence_TestArray_mem_valid_out : std_logic_vector(0 to TESTSEQUENCE_TESTARRAY_MAX_DEPTH-1) := (others => '0');
signal TestSequence_TestArray_mem_data_in, TestSequence_TestArray_mem_data_out : TESTSEQUENCE_TESTARRAY_DATA_TYPE := (others => (others => '0'));
-- TestMap_mem SIGNALS
signal TestMap_mem_addr : std_logic_vector(TESTMAP_ADDR_WIDTH-1 downto 0) := (others => '0');
signal TestMap_mem_read, TestMap_mem_ready_in, TestMap_mem_ready_out, TestMap_mem_valid_in, TestMap_mem_valid_out : std_logic := '0';
signal TestMap_mem_data_in, TestMap_mem_data_out : std_logic_vector(CDR_OCTET_WIDTH+CDR_SHORT_WIDTH-1 downto 0) := (others => '0');
-- TestMap_key_mem SIGNALS
signal TestMap_key_mem_addr : std_logic_vector(TESTMAP_ADDR_WIDTH-1 downto 0) := (others => '0');
signal TestMap_key_mem_read, TestMap_key_mem_ready_in, TestMap_key_mem_ready_out, TestMap_key_mem_valid_in, TestMap_key_mem_valid_out : std_logic := '0';
signal TestMap_key_mem_data_in, TestMap_key_mem_data_out : std_logic_vector(CDR_OCTET_WIDTH-1 downto 0) := (others => '0');
-- TestMap_value_mem SIGNALS
signal TestMap_value_mem_addr : std_logic_vector(TESTMAP_ADDR_WIDTH-1 downto 0) := (others => '0');
signal TestMap_value_mem_read, TestMap_value_mem_ready_in, TestMap_value_mem_ready_out, TestMap_value_mem_valid_in, TestMap_value_mem_valid_out : std_logic := '0';
signal TestMap_value_mem_data_in, TestMap_value_mem_data_out : std_logic_vector(CDR_SHORT_WIDTH-1 downto 0) := (others => '0');
-- TestString_mem SIGNALS
signal TestString_mem_addr : std_logic_vector(TESTSTRING_ADDR_WIDTH-1 downto 0) := (others => '0');
signal TestString_mem_read, TestString_mem_ready_in, TestString_mem_ready_out, TestString_mem_valid_in, TestString_mem_valid_out : std_logic := '0';
@ -271,24 +275,44 @@ begin
);
end generate;
TestMap_mem : entity work.mem_ctrl(arch)
TestMap_key_mem : entity work.mem_ctrl(arch)
generic map (
ADDR_WIDTH => TESTMAP_ADDR_WIDTH,
DATA_WIDTH => CDR_OCTET_WIDTH+CDR_SHORT_WIDTH,
DATA_WIDTH => CDR_OCTET_WIDTH,
MEMORY_DEPTH => TESTMAP_MAX_DEPTH,
MAX_BURST_LENGTH => 1
)
port map (
clk => clk,
reset => reset or abort_mem,
addr => TestMap_mem_addr,
read => TestMap_mem_read,
ready_in => TestMap_mem_ready_in,
valid_in => TestMap_mem_valid_in,
data_in => TestMap_mem_data_in,
ready_out => TestMap_mem_ready_out,
valid_out => TestMap_mem_valid_out,
data_out => TestMap_mem_data_out
addr => TestMap_key_mem_addr,
read => TestMap_key_mem_read,
ready_in => TestMap_key_mem_ready_in,
valid_in => TestMap_key_mem_valid_in,
data_in => TestMap_key_mem_data_in,
ready_out => TestMap_key_mem_ready_out,
valid_out => TestMap_key_mem_valid_out,
data_out => TestMap_key_mem_data_out
);
TestMap_value_mem : entity work.mem_ctrl(arch)
generic map (
ADDR_WIDTH => TESTMAP_ADDR_WIDTH,
DATA_WIDTH => CDR_SHORT_WIDTH,
MEMORY_DEPTH => TESTMAP_MAX_DEPTH,
MAX_BURST_LENGTH => 1
)
port map (
clk => clk,
reset => reset or abort_mem,
addr => TestMap_value_mem_addr,
read => TestMap_value_mem_read,
ready_in => TestMap_value_mem_ready_in,
valid_in => TestMap_value_mem_valid_in,
data_in => TestMap_value_mem_data_in,
ready_out => TestMap_value_mem_ready_out,
valid_out => TestMap_value_mem_valid_out,
data_out => TestMap_value_mem_data_out
);
TestString_mem : entity work.mem_ctrl(arch)
@ -337,18 +361,19 @@ begin
TestSequence_TestWChar_r <= TestSequence_TestWChar_mem_data_out;
TestSequence_TestLongLong_r <= TestSequence_TestLongLong_mem_data_out;
TestSequence_TestLongDouble_r <= TestSequence_TestLongDouble_mem_data_out(CDR_LONG_DOUBLE_WIDTH-1 downto 0);
TestSequence_TestLongDouble_valid_r <= TestSequence_TestLongDouble_mem_data_out(CDR_LONG_DOUBLE_WIDTH);
TestMap_valid <= TestMap_mem_valid_out;
TestMap_key_r <= TestMap_mem_data_out(CDR_OCTET_WIDTH+CDR_SHORT_WIDTH-1 downto CDR_SHORT_WIDTH);
TestMap_value_r <= TestMap_mem_data_out(CDR_SHORT_WIDTH-1 downto 0);
TestSequence_TestLongDouble_opt_r <= TestSequence_TestLongDouble_mem_data_out(CDR_LONG_DOUBLE_WIDTH);
TestMap_valid <= TestMap_key_mem_valid_out and TestMap_value_mem_valid_out;
TestMap_key_r <= TestMap_key_mem_data_out;
TestMap_value_r <= TestMap_value_mem_data_out;
TestString_valid <= TestString_mem_valid_out;
TestString_r <= TestString_mem_data_out;
TestSequence_TestChar_mem_data_in <= TestSequence_TestChar_w;
TestSequence_TestWChar_mem_data_in <= TestSequence_TestWChar_w;
TestSequence_TestLongLong_mem_data_in <= TestSequence_TestLongLong_w;
TestSequence_TestLongDouble_mem_data_in <= TestSequence_TestLongDouble_valid_w & TestSequence_TestLongDouble_w;
TestSequence_TestLongDouble_mem_data_in <= TestSequence_TestLongDouble_opt_w & TestSequence_TestLongDouble_w;
TestSequence_TestArray_mem_data_in <= (others => TestSequence_TestArray_w);
TestMap_mem_data_in <= TestMap_key_w & TestMap_value_w;
TestMap_key_mem_data_in <= TestMap_key_w;
TestMap_value_mem_data_in <= TestMap_value_w;
TestString_mem_data_in <= TestString_w;
-- ###GENERATED END###
@ -395,10 +420,14 @@ begin
TestSequence_TestArray_mem_read <= (others => '0');
TestSequence_TestArray_mem_valid_in <= (others => '0');
TestSequence_TestArray_mem_ready_out <= (others => '0');
TestMap_mem_addr <= (others => '0');
TestMap_mem_read <= '0';
TestMap_mem_valid_in <= '0';
TestMap_mem_ready_out <= '0';
TestMap_key_mem_addr <= (others => '0');
TestMap_key_mem_read <= '0';
TestMap_key_mem_valid_in <= '0';
TestMap_key_mem_ready_out <= '0';
TestMap_value_mem_addr <= (others => '0');
TestMap_value_mem_read <= '0';
TestMap_value_mem_valid_in <= '0';
TestMap_value_mem_ready_out <= '0';
TestString_mem_addr <= (others => '0');
TestString_mem_read <= '0';
TestString_mem_valid_in <= '0';
@ -438,6 +467,7 @@ begin
null;
end case;
else
-- ###GENERATED START###
TestSequence_ready <= TestSequence_TestChar_mem_ready_in and TestSequence_TestWChar_mem_ready_in and TestSequence_TestLongLong_mem_ready_in and TestSequence_TestLongDouble_mem_ready_in;
TestSequence_TestChar_mem_addr <= TestSequence_addr;
TestSequence_TestChar_mem_read <= TestSequence_ren;
@ -464,16 +494,21 @@ begin
if (TestSequence_TestArray_ren = '1') then
TestSequence_addr_latch_next <= TestSequence_addr;
end if;
TestMap_ready <= TestMap_mem_ready_in;
TestMap_mem_addr <= TestMap_addr;
TestMap_mem_read <= TestMap_ren;
TestMap_mem_valid_in <= TestMap_ren or TestMap_wen;
TestMap_mem_ready_out <= TestMap_ack;
TestMap_ready <= TestMap_key_mem_ready_in and TestMap_value_mem_ready_in;
TestMap_key_mem_addr <= TestMap_addr;
TestMap_key_mem_read <= TestMap_ren;
TestMap_key_mem_valid_in <= TestMap_ren or TestMap_wen;
TestMap_key_mem_ready_out <= TestMap_ack;
TestMap_value_mem_addr <= TestMap_addr;
TestMap_value_mem_read <= TestMap_ren;
TestMap_value_mem_valid_in <= TestMap_ren or TestMap_wen;
TestMap_value_mem_ready_out <= TestMap_ack;
TestString_ready <= TestString_mem_ready_in;
TestString_mem_addr <= TestString_addr;
TestString_mem_read <= TestString_ren;
TestString_mem_valid_in <= TestString_ren or TestString_wen;
TestString_mem_ready_out <= TestString_ack;
-- ###GENERATED END###
end if;
when WRITE_PAYLOAD_HEADER =>
if (LITTLE_ENDIAN = '0') then
@ -482,6 +517,9 @@ begin
data_out_latch_next <= CDR_LE & x"0000";
end if;
stage_next <= PUSH;
-- ###GENERATED START###
encode_stage_next <= WRITE_ID;
-- ###GENERATED END###
when PUSH =>
-- Mark Last Word
if (finalize_payload = '1') then
@ -826,21 +864,23 @@ begin
case (cnt) is
-- GET
when 0 =>
TestMap_mem_addr <= std_logic_vector(to_unsigned(TestMap_cnt,TESTMAP_ADDR_WIDTH));
TestMap_mem_valid_in <= '1';
TestMap_mem_read <= '1';
TestMap_key_mem_addr <= std_logic_vector(to_unsigned(TestMap_cnt,TESTMAP_ADDR_WIDTH));
TestMap_key_mem_valid_in <= '1';
TestMap_key_mem_read <= '1';
-- Memory Operation Guard
if (TestMap_mem_ready_in = '1') then
if (TestMap_key_mem_ready_in = '1') then
cnt_next <= cnt + 1;
end if;
-- WRITE
when 1 =>
TestMap_key_mem_ready_out <= '1';
-- Memory Operation Guard
if (TestMap_mem_valid_out = '1') then
data_out_latch_next <= write_sub_vector(data_out_latch, endian_swap(LITTLE_ENDIAN, TestMap_mem_data_out(CDR_OCTET_WIDTH+CDR_SHORT_WIDTH-1 downto CDR_SHORT_WIDTH)), to_integer(align_offset(1 downto 0)), TRUE);
if (TestMap_key_mem_valid_out = '1') then
data_out_latch_next <= write_sub_vector(data_out_latch, endian_swap(LITTLE_ENDIAN, TestMap_key_mem_data_out), to_integer(align_offset(1 downto 0)), TRUE);
align_offset_next <= align_offset + 1;
encode_stage_next <= WRITE_TESTMAP_VALUE;
encode_stage_next <= WRITE_TESTMAP_VALUE;
cnt_next <= 0;
-- DES: Needed for ALIGN_1
-- Need to fetch next Word
@ -857,20 +897,33 @@ begin
target_align_next <= ALIGN_2;
stage_next <= ALIGN_STREAM;
else
TestMap_mem_ready_out <= '1';
-- Memory Operation Guard
if (TestMap_mem_valid_out = '1') then
data_out_latch_next <= write_sub_vector(data_out_latch, endian_swap(LITTLE_ENDIAN, TestMap_mem_data_out(CDR_SHORT_WIDTH-1 downto 0)), to_integer(align_offset(1 downto 1)), TRUE);
align_offset_next <= align_offset + 2;
case (cnt) is
-- GET
when 0 =>
TestMap_value_mem_addr <= std_logic_vector(to_unsigned(TestMap_cnt,TESTMAP_ADDR_WIDTH));
TestMap_value_mem_valid_in <= '1';
TestMap_value_mem_read <= '1';
-- Memory Operation Guard
if (TestMap_value_mem_ready_in = '1') then
cnt_next <= cnt + 1;
end if;
-- WRITE
when 1 =>
TestMap_value_mem_ready_out <= '1';
-- Memory Operation Guard
if (TestMap_value_mem_valid_out = '1') then
data_out_latch_next <= write_sub_vector(data_out_latch, endian_swap(LITTLE_ENDIAN, TestMap_value_mem_data_out), to_integer(align_offset(1 downto 1)), TRUE);
align_offset_next <= align_offset + 2;
encode_stage_next <= TESTMAP_MEMBER_END;
encode_stage_next <= TESTMAP_MEMBER_END;
-- DES: Needed for ALIGN_1
-- Need to fetch next Word
if(align_offset(1 downto 1) = "1") then
stage_next <= PUSH;
end if;
end if;
-- Need to fetch next Word
if(align_offset(1 downto 1) = "1") then
stage_next <= PUSH;
end if;
end if;
when others =>
end case;
end if;
when TESTMAP_MEMBER_END =>
-- All Elements processed
@ -910,7 +963,7 @@ begin
-- OPTIONAL HEADER
when 0 =>
-- Optional Available
if (TestUnion_valid = '1') then
if (TestUnion_opt = '1') then
case (TestUnion_d) is
when TESTUNION_LONGU_D =>
-- Member ID 4, Length 8
@ -1010,6 +1063,7 @@ begin
-- Empty Sequence
if (unsigned(TestString_len) = 0) then
-- DONE
stage_next <= PUSH;
finalize_payload_next <= '1';
encode_done <= '1';
else

4
src/Tests/test_md5.vhd → src/Tests/test_key_hash_generator.vhd
View File

@ -2,7 +2,7 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture arch of md5_calculator is
architecture arch of key_hash_generator is
type STAGE_TYPE is (IDLE, GEN_CHECKSUM, FINALIZE);
@ -13,7 +13,7 @@ architecture arch of md5_calculator is
begin
done <= done_sig;
hash_out <= checksum;
key_hash <= checksum;
checksum_prc : process(all)
begin

4
src/Tests/testbench.pro
View File

@ -82,12 +82,12 @@ analyze Level_0/L0_dds_reader_test5_arzkriu.vhd
analyze Level_0/L0_dds_reader_test6_arzkriu.vhd
analyze Level_0/L0_dds_reader_test7_arzkriu.vhd
analyze ../key_holder.vhd
analyze ../md5_calculator.vhd
analyze ../key_hash_generator.vhd
analyze Type2_package.vhd
analyze Type2_reader_wrapper.vhd
analyze Type2_writer_wrapper.vhd
analyze Type2_key_holder.vhd
analyze test_md5.vhd
analyze test_key_hash_generator.vhd
analyze Level_1/L1_Type2_wrapper_test1.vhd
analyze Level_1/L1_Type2_wrapper_test2.vhd
analyze Level_1/L1_Type2_key_holder_test1.vhd

4
src/md5_calculator.vhd → src/key_hash_generator.vhd
View File

@ -2,7 +2,7 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity md5_calculator is
entity key_hash_generator is
port (
clk : in std_logic;
reset : in std_logic;
@ -15,7 +15,7 @@ entity md5_calculator is
ready_in : out std_logic;
last_word_in : in std_logic;
hash_out : out std_logic_vector(127 downto 0);
key_hash : out std_logic_vector(127 downto 0);
done : out std_logic
);
end entity;