Greek
16bd4558de
* rtps_handler
...
- Handle case where packet end = submessage end (Avoid extra stage switches)
- Fix last_word_out
- Fix case where rd and empty are both high (INFO_TS)
* Modify Endpoint Frame format of GAP
- Add dummy word to avoid complexity
* rtps_handler Testbench
- Add check for last_word_out
2020-11-21 21:10:26 +01:00
Greek
e624ba4bac
* Added rtps_handler_test2
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- Complete and Passing
* Added timeout watchdogs
* Switched to OSVVM Logging
* Added Test Config
2020-11-18 11:24:03 +01:00
Greek
9b4a2ed073
* Various Bug Fixes in rtps_handler
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* rtps_handler_test1 Complete and Passing
2020-11-17 15:26:20 +01:00
Greek
9c95e58e32
* Added OSVVM Library as Submodule
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* Merged stimulus generation procedures to one single procedure
* Integrated OSVVM into testbench
* Generated OSVVM Project Script File
* Various Bug Fixes to compile testbench
2020-11-15 20:34:39 +01:00
Greek
a792cb7d8a
* Added testbench package
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* First rtps_handler Testbench
NOTE: Not tested/compiled.
2020-11-13 11:52:38 +01:00
Greek
c68caec626
* Package update
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- New functions
- Renames
- New Definitions
* rtps_handler overhaul
- Validity Check for Submessages
- OVERREAD Guard
- Info Timestamp parsed and sent to Endpoints
2020-11-13 11:44:17 +01:00
Greek
9acd98b32e
* Update .gitignore
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* Split rtps_package
2020-11-02 14:39:27 +01:00
Greek
ee9746272f
* Before Quartus upgrade
2020-10-31 20:54:34 +01:00
Greek
51c90129c4
* Fix "MATCH_DEST_ENDPOINT" in rtps_handler
2020-10-29 15:18:28 +01:00
Greek
ce72c147a4
* Re-wrote "rtps_ahandler"
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- Compiles
2020-10-29 11:31:41 +01:00
Greek
d61b9dc80a
* rtps_builtin_endpoint compiles
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* Single port RAM implementation for Altera
* Added Altera doc
2020-10-26 23:43:54 +01:00
Greek
63c8c8dccc
* Restructure, cleaning and final documentation in builtin_endpoint
2020-10-25 23:32:24 +01:00
Greek
86a6d85be4
* rtps_package compiles
2020-10-24 22:51:50 +02:00
Greek
74515d0ecc
* Code cleanup
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* Varius fixes
* Code Comment
2020-10-24 17:00:52 +02:00
Greek
73dbc87c08
* Heartbeat sending
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* Liveliness Assertion
* Participant Announcement
* Colapse all Header sending into single stage, remove RTPS header from pre-generated data
2020-10-22 15:00:35 +02:00
Greek
7dd316bbdd
* Implemented GAP handling
2020-10-21 21:23:08 +02:00
Greek
b5b71bbfa9
* Implemented Participant Message Handling
2020-10-21 19:41:23 +02:00
Greek
127b371004
* Initialise all counters with 0
2020-10-21 17:30:39 +02:00
Greek
69da90be20
* Finished ACKNACK and HEARTBEAT handling
2020-10-21 17:04:08 +02:00
Greek
b79e631ac6
* tmp (Before Buffer reorder)
2020-10-21 12:38:51 +02:00
0ec0003eb3
* Fix ASCII Diagrams
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* Constant RTPS Message generation (Endpoint and Participant)
2020-10-12 07:25:56 +02:00
bcdf8f0ed9
* Switch to single Domain ID
2020-10-07 13:12:04 +02:00
809810f207
* Change builtin-endpoint to "last_word" System
2020-10-06 11:02:31 +02:00
aed60f9b01
* Finish Memory FSM
2020-10-06 08:35:31 +02:00
e6e4094583
* Endoint Match/Unmatch
2020-10-04 08:25:35 +02:00
aaae545c8b
* Partly implemented rtps_builtin_endpoint
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* Modify rtps_handler
* Modify rtps_package
2020-09-22 21:04:29 +02:00
4a6b19ef25
* Add Documentation/Commenting
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* Update test project
2020-09-22 21:01:28 +02:00
a841a5c07e
* Add Documentation
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- DDS-Xtypes v1.3
- RTPS Implementation Thesis
- DDS Tutorial Slides
- IEEE 1003.2-1992 Standard Interpretation
2020-09-22 20:44:30 +02:00
Greek
721d03ac8b
* Project Restructure
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- SYN Directory divided onto subdirectories depending on target
Board
* Added DE10-Nano Project
2020-05-29 12:10:07 +02:00
Greek
41f41b6530
* Updated Vivado Project
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* Synthesis fixes in RTPS Handler
2020-05-27 17:55:54 +02:00
Greek
052a4054b9
* Added Documentation in RTPS
2020-05-24 18:28:57 +02:00
Greek
9ab7d79d87
* Added Documentation
...
- UDP Protocol
* Added Synthesis Report for IPv4 Parser with different buffer sizes
* Small fixes in IPv4 Handler
* Added addsub Entity
* Added Checksum entity
* Implemented RTPS Parser
- Compiles in Modelsim
* Backup Version of RTPS Parser to extract and implement UDP Checksuming
* Updated RTPS Package
* Added VHDL comilation test file
2020-05-24 13:08:03 +02:00
Greek
10cda546bf
* Add documentation
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- IPv4 RFC
- FPGA Network Stack Master Thesis
* Updated .gitignore
* Added Single Port RAM
- Xillinx Specific
* Added IPv4 Parser
- Dynamic Re-assembly Buffer selection
- Main entity documentation missing
- Synthesized, but not tested or simulated
* Added Vivado (Zedboard) project for synthesis testing
2020-05-13 13:37:23 +02:00
Greek
b118482e63
* Added DDS/RTPS Documentation
...
* Added initial constant package
2020-05-10 19:31:49 +02:00