Greek
3a1aeb818e
Remove TRANSPORT_PRIORITY_QOS
...
According to RTPS Specification, the TRANSPORT_PRIORITY_QOS is only for
Topic Data.
2021-12-15 16:30:31 +01:00
Greek
02f0fbfb98
Add PREFER_MULTICAST generic in rtps_buildin_endpoint
...
Until now the rtps_builtin_endpoint was using the last parsed Locator as
the Locator of choice.
The rtps_builtin_endpoint was extended with a PREFER_MULTICAST boolean
generic that allows to influence which locators are used.
Test1 of rtps_builtin_endpoint was split in two, to test both settings
of the generic.
2021-12-13 14:31:33 +01:00
Greek
4841d0a6bb
Add synthesis Test6
2021-12-09 23:32:18 +01:00
Greek
f13d28d811
Add/Modify synthesis entities to synthesize test_loopback
2021-12-09 23:32:08 +01:00
5d9acb6f41
Add directive to allow QSYS Compilation
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QSYS does not allow to change the VHDL version of processed files.
All respective files have to have a comment directive forcing the VHDL version.
2021-12-09 19:44:38 +01:00
Greek
0ede0537b7
Add test entities to test PL-PS communication
2021-12-09 19:44:37 +01:00
Greek
b47d409f13
Make codebase Quartus synthesizable
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Remove non-Quartus-supported VHDL 2008 features.
Remove inferred Latches.
Add test Entities to see resulting hw synthesis of various code
segments.
2021-12-07 13:05:24 +01:00
Greek
35743b6f19
Add and update doc
...
Added documentation for MD5 HASH Cacluclation
Updated TODO and REF with new design decisions
2021-01-11 12:06:18 +01:00
Greek
c68caec626
* Package update
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- New functions
- Renames
- New Definitions
* rtps_handler overhaul
- Validity Check for Submessages
- OVERREAD Guard
- Info Timestamp parsed and sent to Endpoints
2020-11-13 11:44:17 +01:00
Greek
9acd98b32e
* Update .gitignore
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* Split rtps_package
2020-11-02 14:39:27 +01:00
Greek
ee9746272f
* Before Quartus upgrade
2020-10-31 20:54:34 +01:00
Greek
51c90129c4
* Fix "MATCH_DEST_ENDPOINT" in rtps_handler
2020-10-29 15:18:28 +01:00
Greek
ce72c147a4
* Re-wrote "rtps_ahandler"
...
- Compiles
2020-10-29 11:31:41 +01:00
Greek
d61b9dc80a
* rtps_builtin_endpoint compiles
...
* Single port RAM implementation for Altera
* Added Altera doc
2020-10-26 23:43:54 +01:00
Greek
63c8c8dccc
* Restructure, cleaning and final documentation in builtin_endpoint
2020-10-25 23:32:24 +01:00
Greek
b79e631ac6
* tmp (Before Buffer reorder)
2020-10-21 12:38:51 +02:00
4a6b19ef25
* Add Documentation/Commenting
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* Update test project
2020-09-22 21:01:28 +02:00
Greek
721d03ac8b
* Project Restructure
...
- SYN Directory divided onto subdirectories depending on target
Board
* Added DE10-Nano Project
2020-05-29 12:10:07 +02:00
Greek
41f41b6530
* Updated Vivado Project
...
* Synthesis fixes in RTPS Handler
2020-05-27 17:55:54 +02:00
Greek
9ab7d79d87
* Added Documentation
...
- UDP Protocol
* Added Synthesis Report for IPv4 Parser with different buffer sizes
* Small fixes in IPv4 Handler
* Added addsub Entity
* Added Checksum entity
* Implemented RTPS Parser
- Compiles in Modelsim
* Backup Version of RTPS Parser to extract and implement UDP Checksuming
* Updated RTPS Package
* Added VHDL comilation test file
2020-05-24 13:08:03 +02:00
Greek
10cda546bf
* Add documentation
...
- IPv4 RFC
- FPGA Network Stack Master Thesis
* Updated .gitignore
* Added Single Port RAM
- Xillinx Specific
* Added IPv4 Parser
- Dynamic Re-assembly Buffer selection
- Main entity documentation missing
- Synthesized, but not tested or simulated
* Added Vivado (Zedboard) project for synthesis testing
2020-05-13 13:37:23 +02:00
