rtps-fpga

greek64/rtps-fpga

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Commit Graph

Author	SHA1	Message	Date
Greek	52bd4053d1	Add mem_ctrl Level 0 Test 1 mem_ctrl fixed and testbench implemented	2021-02-17 14:01:49 +01:00
Greek	d54bf55b46	Redo Memory Interface of RTPS Endpoint The Memory Control Process is made more generic (with less specialised code), to allow the main process more control. I.e. all Memory Frame Fields are individually addressable (during GET and UPDATE). The RAM instance is hidden behind a Memory Controller with Flow Control Signals, allowing easy future integration to different Memory Interfaces (e.g. AXI Lite).	2021-02-02 00:04:34 +01:00

Author

SHA1

Message

Date

Greek

52bd4053d1

Add mem_ctrl Level 0 Test 1

mem_ctrl fixed and testbench implemented

2021-02-17 14:01:49 +01:00

Greek

d54bf55b46

Redo Memory Interface of RTPS Endpoint

The Memory Control Process is made more generic (with less specialised
code), to allow the main process more control. I.e. all Memory Frame
Fields are individually addressable (during GET and UPDATE).
The RAM instance is hidden behind a Memory Controller with Flow Control
Signals, allowing easy future integration to different Memory Interfaces
(e.g. AXI Lite).

2021-02-02 00:04:34 +01:00

2 Commits