7 Commits

Author	SHA1	Message	Date
Greek	4896929e1b	code refactoring	2021-12-09 19:44:40 +01:00
Greek64	5d9acb6f41	Add directive to allow QSYS Compilation ... QSYS does not allow to change the VHDL version of processed files. All respective files have to have a comment directive forcing the VHDL version.	2021-12-09 19:44:38 +01:00
Greek	6e20b8958d	Add VHDL configuration for single_port_ram and FWFT_FIFO ... Allow single_port_ram and FWFT_FIFO to have Altera specific architectures.	2021-12-09 19:43:56 +01:00
Greek	63465e8e30	Remove default signal initialization from entire codebase	2021-11-19 18:50:18 +01:00
Greek	e87d84ba24	Modify ports of rtps_builtin_endpoint according to port naming convention ... The ports to rtps_out from the rtps_reader and rtps_writer entities were also modified to apply a uniform naming.	2021-11-18 16:44:42 +01:00
Greek	52bd4053d1	Add mem_ctrl Level 0 Test 1 ... mem_ctrl fixed and testbench implemented	2021-02-17 14:01:49 +01:00
Greek	d54bf55b46	Redo Memory Interface of RTPS Endpoint ... The Memory Control Process is made more generic (with less specialised code), to allow the main process more control. I.e. all Memory Frame Fields are individually addressable (during GET and UPDATE). The RAM instance is hidden behind a Memory Controller with Flow Control Signals, allowing easy future integration to different Memory Interfaces (e.g. AXI Lite).	2021-02-02 00:04:34 +01:00