df67cf626d
Update and resynthesize all examples in GHRD Project
2023-07-30 16:09:55 +02:00
4c51a3944a
Add UDP loopback in De10-Nano GHRD Project and generate output files
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The UDP loopback just reads from the input FIFO, reverses src and destination
addresses, and writes back to the output FIFO.
This can be used to measure the throughput of the HPS-FPGA communication
2023-07-29 12:23:06 +02:00
a20890e126
Modify test_top and config for ROS RTT Test and add to DE10-Nano Project
2023-07-27 13:23:52 +02:00
70f9a08802
Add/Modify synthesis entities to synthesize Fibonacci_ros_action_server
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NOTE: Synthesized design does not fit
2022-03-13 12:43:12 +01:00
Greek
f63fccdcc1
Add/Modify synthesis entities to synthesize AddTwoInts_srv_server
2022-01-29 11:12:32 +01:00
Greek
f13d28d811
Add/Modify synthesis entities to synthesize test_loopback
2021-12-09 23:32:08 +01:00
5d9acb6f41
Add directive to allow QSYS Compilation
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QSYS does not allow to change the VHDL version of processed files.
All respective files have to have a comment directive forcing the VHDL version.
2021-12-09 19:44:38 +01:00
Greek
0ede0537b7
Add test entities to test PL-PS communication
2021-12-09 19:44:37 +01:00
