Greek64 6724156e72 TIMING CLOSURE: Split main FSM in dds_reader ... The sequential logic of the main FSM in dds_reader was just to big to pass the timing requirement of 50 MHz. All the DDS READ/TAKE relevant states were removed from the main FSM, and added to a seperate read FSM. This reduces the state numberes and state tarnsition logic of the main FSM, allowing it to pass the timing requirements.		2022-04-14 14:27:09 +02:00
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DE10-Nano	Convert dds_reader to Vector Endpoint	2022-04-10 11:04:59 +02:00
Zedboard	* Update .gitignore	2020-11-02 14:39:27 +01:00
dds_reader_syn.vhd	TIMING CLOSURE: Split main FSM in dds_reader	2022-04-14 14:27:09 +02:00
dds_writer_syn.vhd	Convert dds_writer to Vector Endpoint	2022-04-10 11:04:02 +02:00
rtps_reader_syn.vhd	code refactoring	2022-04-05 17:20:32 +02:00
rtps_writer_syn.vhd	code refactoring	2022-04-05 17:20:32 +02:00
syn_config.vhd	Add MAX_PAYLOAD_SIZE to Endpoint Config Record	2022-01-25 17:58:14 +01:00
syn_ros_action_config.vhd	Add/Modify synthesis entities to synthesize Fibonacci_ros_action_server	2022-03-13 12:43:12 +01:00
syn_ros_service_config.vhd	Add ROS Action glue logic	2022-03-08 14:03:39 +01:00
test2.vhd	Add directive to allow QSYS Compilation	2021-12-09 19:44:38 +01:00
test3.vhd	Add directive to allow QSYS Compilation	2021-12-09 19:44:38 +01:00
test4.vhd	Add directive to allow QSYS Compilation	2021-12-09 19:44:38 +01:00
test5.vhd	Add directive to allow QSYS Compilation	2021-12-09 19:44:38 +01:00
test6.vhd	Add synthesis Test6	2021-12-09 23:32:18 +01:00
test7.vhd	Add multipier implementation	2022-03-09 15:36:32 +01:00
test_fpga.vhd	Add/Modify synthesis entities to synthesize test_loopback	2021-12-09 23:32:08 +01:00
test_package.vhd	Add synthesis Test6	2021-12-09 23:32:18 +01:00
test_top.vhd	Add/Modify synthesis entities to synthesize Fibonacci_ros_action_server	2022-03-13 12:43:12 +01:00
test.vhd	Add directive to allow QSYS Compilation	2021-12-09 19:44:38 +01:00
top.sdc	Add/Modify synthesis entities to synthesize test_loopback	2021-12-09 23:32:08 +01:00