Greek
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aa53591056
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* Update doc
- Add Xillybus doc
- Add additional 7-series doc
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2020-04-26 00:34:08 +02:00 |
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Greek
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7392d9f72f
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* Add library/macro relevant documentation
* Implemented closed feedback loop
- Scaler
- Dealy Line
- Add Sub
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2020-04-03 17:50:25 +02:00 |
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Greek
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e1ffa99874
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* Added clock generator for 20Mhz sclk
* Added top entiry
* Added constraints file
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2020-04-01 14:14:14 +02:00 |
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Greek
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a28aab25fa
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* Added Zynq 7 documentation
* Updated sync processes for async reset
* Implemented simple open loop design
- Added testbench and .do file
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2020-04-01 14:12:04 +02:00 |
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Greek
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2beb7f4b4d
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* .gitignore update
* Added implementation for PMOD-AD1 Controller including testbench
* Added implementation for PMOD-DA3 Controller including testbench
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2020-03-12 20:20:35 +01:00 |
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Greek
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d82505b819
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* Initial Commit
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2020-03-12 15:38:06 +01:00 |
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