BUG FIX: Change Fibonacci_ros_action_server memory operation guard
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@ -865,7 +865,7 @@ begin
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-- WRITE
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when 1 =>
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-- Memory Operation Guard
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if (result_seq_ready = '1' and r_seq_mem_valid_out(to_integer(unsigned(r_index))) = '1') then
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if (seq_ready_sig = '1' and r_seq_mem_valid_out(to_integer(unsigned(r_index))) = '1') then
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seq_addr_sig <= std_logic_vector(to_unsigned(seq_cnt,R_RR_SEQ_ADDR_WIDTH));
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seq_wen_sig <= '1';
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seq_w_sig <= r_seq_mem_data_out(to_integer(unsigned(r_index)));
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