4c51a3944a
Add UDP loopback in De10-Nano GHRD Project and generate output files
...
The UDP loopback just reads from the input FIFO, reverses src and destination
addresses, and writes back to the output FIFO.
This can be used to measure the throughput of the HPS-FPGA communication
2023-07-29 12:23:06 +02:00
a20890e126
Modify test_top and config for ROS RTT Test and add to DE10-Nano Project
2023-07-27 13:23:52 +02:00
d8647ddec9
Move SDC file specific to DE10-Nano Quartus project to project root
2023-07-23 14:12:50 +02:00
d388e29c36
Convert dds_reader to Vector Endpoint
2022-04-10 11:04:59 +02:00
5e7ea79887
Convert dds_writer to Vector Endpoint
2022-04-10 11:04:02 +02:00
f6fec48a0e
Convert rtps_writer to Vector Endpoint
...
rtps_writer now can be configured to simulate multiple endpoints. All
Testbenched were modified to reflect and test this change.
Packages were extended with array definitions.
2022-04-05 17:18:07 +02:00
70f9a08802
Add/Modify synthesis entities to synthesize Fibonacci_ros_action_server
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NOTE: Synthesized design does not fit
2022-03-13 12:43:12 +01:00
7c423467bc
Add multipier implementation
2022-03-09 15:36:32 +01:00
Greek
f63fccdcc1
Add/Modify synthesis entities to synthesize AddTwoInts_srv_server
2022-01-29 11:12:32 +01:00
Greek
59bff52832
Rename rtps_builtin_endpoint to rtps_discovery_module
2022-01-16 18:12:11 +01:00
Greek
e0280ea490
Define RTPS/DDS Configuration in record type
2022-01-16 16:16:58 +01:00
Greek
3ee4769c52
Rename *_wrapper to *_interface
...
Since the Type Specific user facing entities did not actually wrap the
DDS entities, but connected to them through port signals, a more
semantically correct name would be "interface", since they are the user
facing interface of the DDS entities.
2022-01-03 14:25:27 +01:00
Greek
4841d0a6bb
Add synthesis Test6
2021-12-09 23:32:18 +01:00
Greek
f13d28d811
Add/Modify synthesis entities to synthesize test_loopback
2021-12-09 23:32:08 +01:00
Greek
0ede0537b7
Add test entities to test PL-PS communication
2021-12-09 19:44:37 +01:00
Greek
b47d409f13
Make codebase Quartus synthesizable
...
Remove non-Quartus-supported VHDL 2008 features.
Remove inferred Latches.
Add test Entities to see resulting hw synthesis of various code
segments.
2021-12-07 13:05:24 +01:00
Greek
35743b6f19
Add and update doc
...
Added documentation for MD5 HASH Cacluclation
Updated TODO and REF with new design decisions
2021-01-11 12:06:18 +01:00
Greek
c68caec626
* Package update
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- New functions
- Renames
- New Definitions
* rtps_handler overhaul
- Validity Check for Submessages
- OVERREAD Guard
- Info Timestamp parsed and sent to Endpoints
2020-11-13 11:44:17 +01:00
Greek
9acd98b32e
* Update .gitignore
...
* Split rtps_package
2020-11-02 14:39:27 +01:00
Greek
ee9746272f
* Before Quartus upgrade
2020-10-31 20:54:34 +01:00
Greek
51c90129c4
* Fix "MATCH_DEST_ENDPOINT" in rtps_handler
2020-10-29 15:18:28 +01:00
Greek
ce72c147a4
* Re-wrote "rtps_ahandler"
...
- Compiles
2020-10-29 11:31:41 +01:00
Greek
d61b9dc80a
* rtps_builtin_endpoint compiles
...
* Single port RAM implementation for Altera
* Added Altera doc
2020-10-26 23:43:54 +01:00
Greek
63c8c8dccc
* Restructure, cleaning and final documentation in builtin_endpoint
2020-10-25 23:32:24 +01:00
Greek
b79e631ac6
* tmp (Before Buffer reorder)
2020-10-21 12:38:51 +02:00
4a6b19ef25
* Add Documentation/Commenting
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* Update test project
2020-09-22 21:01:28 +02:00
Greek
721d03ac8b
* Project Restructure
...
- SYN Directory divided onto subdirectories depending on target
Board
* Added DE10-Nano Project
2020-05-29 12:10:07 +02:00
