cd49506685
* Added C program to read debug info
2020-04-28 13:31:08 +02:00
c60bcd97f6
* Add C Program to write configuration
2020-04-28 12:18:08 +02:00
Greek
a5c68d1fea
* Add documentation
...
- Zedboard Rev.D Errata
* Add debug leds to top entity
* Pin mapping
2020-04-27 13:41:10 +02:00
Greek
11532daee2
* Modify xillinux vivado project
...
- Remove PS-GPIO
2020-04-26 17:53:15 +02:00
Greek
bb07d0a072
* Modify xillinux vivado project
...
- Add custom xillybus IP core to vivado design
- Add feedback_top
TODO: Remove PS_GPIO and connect custom pins
2020-04-26 17:36:25 +02:00
Greek
4fc3cfb9a3
* Update docs
...
- Download correct 7-series reference
* Add design top entity
* Add synchronizer
* Fix syntax, synth errors
2020-04-26 14:34:34 +02:00
Greek
9818d0d27a
* Added Xillybus demo project
2020-04-26 11:42:06 +02:00
Greek
779cd73e8d
* Moved config/constants to central package
...
* Made cap of addsub selectable via signal
* Added debug reporting
- MAX ADC Input 1
- MAX ADC Input 2
- MAX Scaler output
- MAX DAC Output
* Added Async FIFO
* Added Simple Dual Port RAM
* Added Feedback Controller
* Added Xillybus Link
* Moved testbenches to seperate directory
2020-04-26 11:35:46 +02:00
Greek
aa53591056
* Update doc
...
- Add Xillybus doc
- Add additional 7-series doc
2020-04-26 00:34:08 +02:00
Greek
7392d9f72f
* Add library/macro relevant documentation
...
* Implemented closed feedback loop
- Scaler
- Dealy Line
- Add Sub
2020-04-03 17:50:25 +02:00
Greek
e1ffa99874
* Added clock generator for 20Mhz sclk
...
* Added top entiry
* Added constraints file
2020-04-01 14:14:14 +02:00
Greek
a28aab25fa
* Added Zynq 7 documentation
...
* Updated sync processes for async reset
* Implemented simple open loop design
- Added testbench and .do file
2020-04-01 14:12:04 +02:00
Greek
2beb7f4b4d
* .gitignore update
...
* Added implementation for PMOD-AD1 Controller including testbench
* Added implementation for PMOD-DA3 Controller including testbench
2020-03-12 20:20:35 +01:00
Greek
d82505b819
* Initial Commit
2020-03-12 15:38:06 +01:00
