Update the Altera implemenation of the FWFT FIFO to allow write
and read on the smae cycle when the FIFO is full.
This is a requirement for the moving_average implementation.
Add a configurable moving_average implementaion, that has a configurable
window size and is enable triggered.
Also add a moving_average_wrapper that instantiates 2 moving_average instances
(an inner and an outer) to lower the memory resource requirement for large
window sizes. Effective window size is OUTER*INNER, whereas the resources are
only OUTER+INNER. A trigger signal signals when the average is "valid".
Accompanying testebench was also implemented.
The DDS Writer was expecting the user to provide the serialized key
on DISPOSE/UNREGISTER operations. The user should have no direct
interaction with the serialized key.
The operation flow was changed to expect the normal payload from the
user, push it to the Key Holder, and the calculate the serialized key.
The stage that was responsible for simutanously pushing the input to
payload memory and/or the Key Holder was simplified, and the decode
error signal of the Key Holder is now handled.
The last two changes (simplified stage and decode error handling)
were also ported to the DDS Reader.
During testing a scenario arose, where a toggling in the last_word
signal lane while the rest of the signals were not valid was falsely
latched.
All entities with "last_word_in" latches were modifies to only latch
the signal when in valid state.
The ready/valid Signals were missing from the DDS Reader and Writer Interfaces,
preventing the user from effectively using non-Type dependent operations
(like GET_OFFERED_DEADLINE_MISSED_STATUS).
The L1_Type1_test1 was extended to test for this non-type dependent operation.
Fixed Updated Template-, Type1-, and Type2-key_holder to reset the
decode_error signal when a new PUSH_* operation is initiated.
Testbenches are extended to test foe decode_error and its reset.
The server could at any time reset and sever the connection of the user to the
result memory, that could lead to the user indefenitely waiting for a droped
memory read request.
The server now only sever the connection when the result memory has no pending
requests.
L1_Fibanacci_ros_ation_server_test1 and L1_Fibanacci_ros_ation_server_test2
are exetnded to test the fix.
In case of nested collections in a WRITER Interface, the length of the
collection is latched into memories, but the output is not made available
to the user. Since the signal is lacthed either way, making the stored
value also available to the user gives more flexibility to the user.
Even with the previous commits, there still exist race conditions in
which if the Cyclone DDS implementation receives the initial HEARTBEAT
after the message has been sent, it is silently dropped (Volatile behaviour).
And since the Cyclone DDS implementation is ignoring HEARTBEATs of
yet unmatched endpoints (which is what happens to our init HEARTBEAT),
the best way to counter this is to just wait after the reception of the
first Cyclone DDS message (which signifies that it has matched all our
endpoints) until the HEARTBEAT timeout has also sent the respective
initial HEARTBEATs.
The sequential logic of the main FSM in dds_reader was just to big to
pass the timing requirement of 50 MHz.
All the DDS READ/TAKE relevant states were removed from the main FSM,
and added to a seperate read FSM. This reduces the state numberes and
state tarnsition logic of the main FSM, allowing it to pass the timing
requirements.
rtps_writer now can be configured to simulate multiple endpoints. All
Testbenched were modified to reflect and test this change.
Packages were extended with array definitions.
An internal signal was initialized wrongly, and due to various
other reasons (testbench bug, to_integer conversion bug) was not picked
up by the testbenches.
