Another scaling factor was added and both input signals can now be
independenly scaled. In Single Input Mode only Input 1 is passed to the
output (negated if configured as negative feddback). In double input
mode Input 2 is added/subtracted from Input 1 (in1 +/- in2). The delay
line is only applied to Input 2.
Addsub was removed from the design (all Additions and Subtractions are
directly implemented in VHDL code).
Config signals were latched to follow the data flow path and prevent
glitches on certain events.
Vivado Project updated.
Single Package containing all needed pre-calculated sine arrays.
General Code Cleanup.
* Add diagram
* Modify counters of PMOD-AD1 and PMOD-DA3 controllers to use less bits
* Increase factor width to 5 bits
- Highest bit is truncated
* Add download directory to git repo
* Made cap of addsub selectable via signal
* Added debug reporting
- MAX ADC Input 1
- MAX ADC Input 2
- MAX Scaler output
- MAX DAC Output
* Added Async FIFO
* Added Simple Dual Port RAM
* Added Feedback Controller
* Added Xillybus Link
* Moved testbenches to seperate directory
