greek64/labor-mst
1
0
Fork 0
Code Issues Releases Activity
31 Commits 2 Branches 3 Tags 1.2 GiB
8658ac24db
Commit Graph

31 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Greek
8658ac24db Update SW 2021-03-28 13:43:31 +02:00
Greek
2f3e03827a Update Diagrams 2021-03-28 13:26:22 +02:00
Greek
e6b05276d8 Major Rewrite of feedback_loop 
Another scaling factor was added and both input signals can now be
independenly scaled. In Single Input Mode only Input 1 is passed to the
output (negated if configured as negative feddback). In double input
mode Input 2 is added/subtracted from Input 1 (in1 +/- in2). The delay
line is only applied to Input 2.
Addsub was removed from the design (all Additions and Subtractions are
directly implemented in VHDL code).
Config signals were latched to follow the data flow path and prevent
glitches on certain events.
Vivado Project updated.
Single Package containing all needed pre-calculated sine arrays.
General Code Cleanup.
 2021-03-28 12:32:56 +02:00
Greek
9d6838aca3 Fix Overflow/Underflow and Delay Line 2021-03-26 23:56:28 +01:00
Greek64
b1f3a5c0bc Fix gen_sine.sh 2021-03-25 13:06:30 +01:00
Greek64
336a393655 Add pre-generated sine arrays 2021-03-25 11:58:07 +01:00
Greek64
19aadb159e Add gen_sine.sh 
Add Shell Script that generates sine wave arrays in VHDL packages.
 2021-03-25 11:57:51 +01:00
Greek64
3f111508c1 Day 2 Labor Fixes 2021-03-24 10:53:49 +01:00
Greek
b6357a993e Fix Scaling Offset 2021-03-24 10:53:49 +01:00
Greek64
abe34fd0fc Day 1 Labor Fixes 2021-03-24 10:53:40 +01:00
Greek
ad89405df7 Update README 2021-03-22 00:21:32 +01:00
Greek
c638cb7191 * Update diagram (No transparency) 
* Fix Markdown table
 2020-04-29 23:53:49 +02:00
Greek
922c7cdb83 * Add Project Description and Documentation (Readme.md) 
* Add diagram
* Modify counters of PMOD-AD1 and PMOD-DA3 controllers to use less bits
* Increase factor width to 5 bits
	- Highest bit is truncated
* Add download directory to git repo
 2020-04-29 20:59:35 +02:00
Greek
29036ded6f * Fix scaler 
- Add generic to select between signed and unsigned
 2020-04-29 17:34:16 +02:00
Greek
89182e8060 * Route sclk for ADC/DAC through controller entity itself 
* Remove ADC/DAC input/outputs constraints
* Fix PMOD-AS1 Controller
	- Invert SCLK
 2020-04-29 14:01:01 +02:00
Greek
131a9b3a6e * Modify PMOD-AS1 testbench 
* Add reference PMOD AD1 controller
	- Including testbench
 2020-04-29 13:28:41 +02:00
Greek
ae928c116b * Fix xillybus-FPGA data ordering 
* Add file explaining custom mapping
 2020-04-28 15:12:31 +02:00
Greek64
cd49506685 * Added C program to read debug info 2020-04-28 13:31:08 +02:00
Greek64
c60bcd97f6 * Add C Program to write configuration 2020-04-28 12:18:08 +02:00
Greek
a5c68d1fea * Add documentation 
- Zedboard Rev.D Errata
* Add debug leds to top entity
* Pin mapping
 2020-04-27 13:41:10 +02:00
Greek
11532daee2 * Modify xillinux vivado project 
- Remove PS-GPIO
 2020-04-26 17:53:15 +02:00
Greek
bb07d0a072 * Modify xillinux vivado project 
- Add custom xillybus IP core to vivado design
	- Add feedback_top
TODO: Remove PS_GPIO and connect custom pins
 2020-04-26 17:36:25 +02:00
Greek
4fc3cfb9a3 * Update docs 
- Download correct 7-series reference
* Add design top entity
* Add synchronizer
* Fix syntax, synth errors
 2020-04-26 14:34:34 +02:00
Greek
9818d0d27a * Added Xillybus demo project 2020-04-26 11:42:06 +02:00
Greek
779cd73e8d * Moved config/constants to central package 
* Made cap of addsub selectable via signal
* Added debug reporting
    - MAX ADC Input 1
    - MAX ADC Input 2
    - MAX Scaler output
    - MAX DAC Output
* Added Async FIFO
* Added Simple Dual Port RAM
* Added Feedback Controller
* Added Xillybus Link
* Moved testbenches to seperate directory
 2020-04-26 11:35:46 +02:00
Greek
aa53591056 * Update doc 
- Add Xillybus doc
	- Add additional 7-series doc
 2020-04-26 00:34:08 +02:00
Greek
7392d9f72f * Add library/macro relevant documentation 
* Implemented closed feedback loop
	- Scaler
	- Dealy Line
	- Add Sub
 2020-04-03 17:50:25 +02:00
Greek
e1ffa99874 * Added clock generator for 20Mhz sclk 
* Added top entiry
* Added constraints file
 2020-04-01 14:14:14 +02:00
Greek
a28aab25fa * Added Zynq 7 documentation 
* Updated sync processes for async reset
* Implemented simple open loop design
	- Added testbench and .do file
 2020-04-01 14:12:04 +02:00
Greek
2beb7f4b4d * .gitignore update 
* Added implementation for PMOD-AD1 Controller including testbench
* Added implementation for PMOD-DA3 Controller including testbench
 2020-03-12 20:20:35 +01:00
Greek
d82505b819 * Initial Commit 2020-03-12 15:38:06 +01:00